Mr. Junya Okude Profile

Junya Okude

at KIOXIA Corp

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Proceedings Article | 22 February 2021 Presentation + Paper

In-line schematic failure analysis technique by defect SEM images

Junya Okude, Chihiro Ida, Kazuhiro Nojima, Akira Hamaguchi

Proceedings Volume 11611, 116110M (2021) https://doi.org/10.1117/12.2583469

KEYWORDS: Computer aided design, Scanning electron microscopy, Failure analysis, Inspection, Optical inspection, Semiconductors, Machine learning, Defect detection

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To fix the root cause of electrical failure chips, we do failure analysis by an electrical test. However, this analysis takes much long time because an electrical test is done after a few months since the defect occurred in in-line processes. To reduce the analysis time, we used the defects detected by in-line optical inspections of post semiconductor process steps. In order to identify the position of the defects that caused the failure, we used to match CAD contour with a DR-SEM (Defect Review-SEM) image contour of the defect. But the “hit rate” of the defect was not so high. Here hit rate is a rate that the defects cause an electrical failure chip. There were two reasons. First, the matching success rate was low because extracting contour from SEM is inaccurate. Second, CAD was a mask pattern and didn’t include the circuit node information, so there was an over-detection such as a short between dummy nodes. We propose a high precision in-line schematic failure analysis technique by machine learning and circuit node information. For matching pixel to pixel, we match Fake-SEM generated by GAN instead of CAD with DR-SEM. Next we make the CAD that is added the defect, and a design verification technique LVS generates circuit diagram. When the defect’s diagram is different from reference, we classify the defect cause an electrical failure. We confirmed that this technique could dramatically improve classification accuracy of the defect of root cause in manufacturing with our memory device.

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