As design rule shrinks, it is essential that the capability to detect smaller and smaller defects should improve. There is considerable effort going on in the industry to enhance immersion lithography using directed self-assembly (DSA) for the 14-nm design node and below. While the process feasibility is demonstrated with DSA, material issues as well as process control requirements are not fully characterized. The chemical epitaxy process is currently the most-preferred process option for frequency multiplication, and it involves new materials at extremely small thicknesses. The image contrast of the lamellar line/space pattern at such small layer thicknesses is a new challenge for optical inspection tools. The study focuses on capability of optical inspection systems to capture DSA unique defects such as dislocations and disclination clusters over the system and wafer noise. The study is also extended to investigate wafer-level data at multiple process steps and to determine the contribution from each process step and materials using defect source analysis methodology. The added defect pareto and spatial distributions of added defects at each process step are discussed.
As design rule shrinks, it is essential that the capability to detect smaller and smaller defects should improve. There is
considerable effort going on in the industry to enhance Immersion Lithography using DSA for 14 nm design node and
below. While the process feasibility is demonstrated with DSA, material issues as well as process control requirements
are not fully characterized. The chemical epitaxy process is currently the most-preferred process option for frequency
multiplication and it involves new materials at extremely small thickness. The image contrast of the lamellar Line/Space
pattern at such small layer thickness is a new challenge for optical inspection tools. In this investigation, the focus is on the capability for optical inspection systems to capture DSA unique defects such as dislocations and disclination clusters over the system and wafer noise. The study is also extended to investigate wafer level data at multiple process steps and determining contribution from each process step and materials using ‘Defect Source Analysis’ methodology. The added defect pareto and spatial distributions of added defects at each process step are discussed.
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