A readout IC (ROIC) designed for high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The ROIC is designed for higher Ge content SiGe microbolometers which have higher detector resistance (~1M Ω) and higher TCR values (~%5.5/K). The ROIC includes column SAR ADCs for on-chip column-parallel analog to digital conversion. SAR ADC architecture is chosen to reduce the overall power consumption. The problem of resistance variation across the bolometers which introduce fixed pattern noise is addressed by setting a tunable reference resistor shared for each column which can be calibrated offline to set the common-mode level. Moreover, column non-uniformity has been reduced through comparator offset compensation in the SAR ADC. The columnwise architecture in this work reduces the number of integrators needed in the architecture and enables 17x17 μm2 pixel sizes. The prototype has been designed and fabricated in 0.25-μm CMOS process.
A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (≥ 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.
A 32x32 prototype of a digital readout IC (DROIC) for medium-wave infrared focal plane arrays (MWIR IR-FPAs) is presented. The DROIC employs in-pixel photocurrent to digital conversion based on a pulse frequency modulation (PFM) loop and boasts a novel feature of off-pixel residue conversion using 10-bit column SAR ADCs. The remaining charge at the end of integration in typical PFM based digital pixel sensors is usually wasted. Previous works employing in-pixel extended counting methods make use of extra memory and counters to convert this left-over charge to digital, thereby performing fine conversion of the incident photocurrent. This results in a low quantization noise and hence keeps the readout noise low. However, focal plane arrays (FPAs) with small pixel pitch are constrained in pixel area, which makes it difficult to benefit from in-pixel extended counting circuitry. Thus, in this work, a novel approach to measure the residue outside the pixel using column -parallel SAR ADCs has been proposed. Moreover, a modified version of the conventional PFM based pixel has been designed to help hold the residue charge and buffer it to the column ADC. In addition to the 2D array of pixels, the prototype consists of 32 SAR ADCs, a timing controller block and a memory block to buffer the residue data coming out of the ADCs. The prototype has been designed and fabricated in 90nm CMOS.
This paper presents the design, modelling and simulation results of silicon/silicon-germanium (Si/SiGe) multi-quantum
well based bolometer detector for uncooled infrared imaging system. The microbolometer is designed to detect light in
the long wave length infrared (LWIR) range from 8 to 14 μm with pixel size of 25 x 25 μm.
The design optimization
strategy leads to achieve the temperature coefficient of resistance (TCR) 4.5%/K with maximum germanium (Ge)
concentration of 50%. The design of microbolometer entirely relies on standard CMOS and MEMS processes which
makes it suitable candidate for commercial infrared imaging systems.
KEYWORDS: Readout integrated circuits, Digital electronics, Signal to noise ratio, Quantization, Analog electronics, Capacitors, Staring arrays, Sensors, Capacitance, Lithium
A 15um pixel pitch digital pixel for LWIR time delay integration (TDI) applications is implemented which occupies one
fourth of pixel area compared to previous digital TDI implementation. TDI is implemented on 8 pixels with
oversampling rate of 2. ROIC provides 16 bits output with 8 bits of MSB and 8 bits of LSB. Pixel can store 75 M
electrons with a quantization noise of 500 electrons. Digital pixel TDI implementation is advantageous over analog
counterparts considering power consumption, chip area and signal-to-noise ratio. Digital pixel TDI ROIC is fabricated
with 0.18um CMOS process. In digital pixel TDI implementation photocurrent is integrated on a capacitor in pixel and
converted to digital data in pixel. This digital data triggers the summation counters which implements TDI addition.
After all pixels in a row contribute, the summed data is divided to the number of TDI pixels(N) to have the actual output
which is square root of N improved version of a single pixel output in terms of signal-to-noise-ratio (SNR).
Digital pixels based on pulse frequency modulation (PFM) employ counting techniques to achieve very high charge
handling capability compared to their analog counterparts. Moreover, extended counting methods making use of leftover
charge (residue) on the integration capacitor help improve the noise performance of these pixels. However, medium
wave infrared (MWIR) focal plane arrays (FPAs) having smaller pixel pitch are constrained in terms of pixel area which
makes it difficult to add extended counting circuitry to the pixel. Thus, this paper investigates the performance of digital
pixels employing off-pixel residue measurement. A circuit prototype of such a pixel has been designed for 15μm pixel
pitch and fabricated in 90nm CMOS. The prototype is composed of a pixel front-end based on a PFM loop. The frontend
is a modified version of conventional design providing a means for buffering the signal that needs to be converted to
a digital value by an off-pixel ADC. The pixel has an integration phase and a residue measurement phase. Measured
integration performance of the pixel has been reported in this paper for various detector currents and integration times.
KEYWORDS: Data transmission, Digital electronics, Resistors, Temperature metrology, Transistors, Clocks, Digital electronic circuits, Standards development, Switches, Cryogenics
This paper presents a mixed-signal LVDS driver in 90 nm CMOS technology. The designed LVDS core is to be used as a data link between Infrared Focal Plane Array (IRFPA) detector end and microprocessor input. Parallel data from 220 pixels of IRFPA is serialized by LVDS driver and read out to microprocessor. It also offers a reduced power consumption rate, high data transmission speed and utilizes dense placement of devices for area efficiency. The entire output driver circuit including input buffer draws 5mA while the output swing is 500mV at power supply of 1.2V for data rate of 6.4Gbps.Total LVDS chip area is 0.79 mm2. Due to these features, the designed LVDS driver is suitable for purposes such as portable, high-speed imaging.
KEYWORDS: Capacitors, Sensors, Readout integrated circuits, Digital electronics, Quantization, Signal to noise ratio, Staring arrays, Long wavelength infrared, Analog electronics, CMOS technology
This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referred noise of ROIC is below 750 rms electron meanwhile power dissipation is appreciably under 30mW. ROIC design is optimized to perform at room as well as cryogenic temperatures. For staring type arrays, a digital pixel architecture relying on coarse quantization with pulse frequency modulation (PFM) and novel approach of extended integration is presented. It can achieve extreme charge handling capacity of 2.04Ge- with 20 bit output resolution and power dissipation below 350 nW in CMOS 90nm technology. Efficient mechanism of measuring the time to estimate the remaining charge on integration capacitor in order to achieve low SNR has employed.
KEYWORDS: Signal to noise ratio, Readout integrated circuits, Cryogenics, Instrument modeling, Long wavelength infrared, Digital electronics, Molybdenum, Temperature metrology, Analog electronics, Sensors
This paper presents and discusses the cryogenic temperature (77K) measurement results of a digital readout integrated circuit (DROIC) for a 32x32 long wavelength infrared pixel sensor array designed in 90nm CMOS process. The chip achieves a signal-to-noise ratio (SNR) of 58dB with a charge handling capacity of 2.03Ge- at cryogenic temperature with 1.3mW of power dissipation. The performance of the readout is discussed in terms of power dissipation, charge handling capacity and SNR considering the fact that the process library models are not optimized for cryogenic temperature operation of the Metal-Oxide-Semiconductor (MOS) devices. These results provide an insight to foresee the design confrontations due to non-optimized device models for cryogenic temperatures particularly for short channel devices
Implementation of a CMOS digital readout integrated circuit (DROIC) based on pixel level digital time delay integration (TDI) for scanning type LWIR focal plane arrays (FPAs) is presented. TDI is implemented on 8 pixels with over sampling rate of 3. Analog signal integrated on integration capacitor is converted to digital domain in pixel, and digital data is transferred to TDI summation counters, where contributions of 8 pixels are added. Output data is 16 bit, where 8 bits are allocated for most significant bits and 8 bits for least significant bits. Control block of the ROIC, which is responsible of generating timing diagram for switches controlling the pixels and summation counters, is realized with VerilogHDL. Summation counters and parallel-to-serial converter to convert 16 bit parallel output data to single bit output are also realized with Verilog HDL. Synthesized verilog netlists are placed&routed and combined with analog under-pixel part of the design. Quantization noise of analog-to-digital conversion is less than 500e-. Since analog signal is converted to digital domain in-pixel, inaccuracies due to analog signal routing over large chip area is eliminated. ROIC is fabricated with 0.18μm CMOS process and chip area is 10mm2. Post-layout simulation results of the implemented design are presented. ROIC is programmable through serial or parallel interface. Input referred noise of ROIC is less than 750 rms electron, while power consumption is less than 30mW. ROIC is designed to perform in cryogenic temperatures.
KEYWORDS: Quantization, Signal to noise ratio, Readout integrated circuits, Capacitance, Clocks, Electrons, Capacitors, Digital electronics, Time metrology, Staring arrays
This paper presents a digital ROIC for staring type arrays with extending counting method to realize very low quantization noise while achieving a very high charge handling capacity. Current state of the art has shown that digital readouts with pulse frequency method can achieve charge handling capacities higher than 3Ge- with quantization noise higher than 1000e-. Even if the integration capacitance is reduced, it cannot be lower than 1-3 fF due to the parasitic capacitance of the comparator. For achieving a very low quantization noise of 161 electrons in a power efficient way, a new method based on measuring the time to measure the remaining charge on the integration capacitor is proposed. With this approach SNR of low flux pixels are significantly increased while large flux pixels can store electrons as high as 2.33Ge-. A prototype array of 32×32 pixels with 30μm pitch is implemented in 90nm CMOS process technology for verification. Measurement results are given for complete readout.
KEYWORDS: Short wave infrared radiation, Sensors, Infrared imaging, Signal to noise ratio, Infrared radiation, Staring arrays, Readout integrated circuits, High dynamic range imaging, Analog electronics, Capacitors
This paper presents novel unit cell architecture for short wave infrared (SWIR) imaging applications. It has two input stages which are CTIA and SFD covering for both respectively low and high light, levels and automatic input stage selection circuitry that chooses best input stage. User can select 2 modes for FPA manual and automatic mode. In manual mode, user can set CTIA or SFD for all pixels according to user needs. In automatic mode, each pixel selects input stage itself according to light level. Light level threshold can be adjusted with reference voltage. Automatic input stage selection for each pixel brings high SNR level and low noise along with highest possible dynamic range for SWIR imaging applications. CMOS 0.18μm technology is used to realize unit cell. In the architecture of unit cell, circuit level techniques are used to optimize layout size.
This paper presents a digital ROIC for staring type arrays with extending counting method to realize very low quantization noise while achieving a very high charge handling capacity. Current state of the art has shown that digital readouts with pulse frequency method can achieve charge handling capacities higher than 3Ge- with quantization noise higher than 1000e-. Even if the integration capacitance is reduced, it cannot be lower than 1-3 fF due to the parasitic capacitance of the comparator. For achieving a very low quantization noise of 200 electrons in a power efficient way, a new method based on measuring the time to measure the remaining charge on the integration capacitor is proposed. With this approach SNR of low flux pixels are significantly increased while large flux pixels can store electrons as high as 2.33Ge-. A prototype array of 32x32 pixels with 30μm pitch is implemented in 90nm CMOS process technology for verification. Simulation results are given for complete readout.
KEYWORDS: Readout integrated circuits, Analog electronics, Digital electronics, Sensors, Capacitance, Signal to noise ratio, Multiplexers, Long wavelength infrared, Amplifiers, Imaging systems
Design of a 90×8 CMOS readout integrated circuit (ROIC) based on pixel level digital time delay integration (TDI) for scanning type LWIR focal plane arrays (FPAs) is presented. TDI is implemented on 8 pixels which improves the SNR of the system with a factor of √8. Oversampling rate of 3 improves the spatial resolution of the system. TDI operation is realized with a novel under-pixel analog-to-digital converter, which improves the noise performance of ROIC with a lower quantization noise. Since analog signal is converted to digital domain in-pixel, non-uniformities and inaccuracies due to analog signal routing over large chip area is eliminated. Contributions of each pixel for proper TDI operation are added in summation counters, no op-amps are used for summation, hence power consumption of ROIC is lower than its analog counterparts. Due to lack of multiple capacitors or summation amplifiers, ROIC occupies smaller chip area compared to its analog counterparts. ROIC is also superior to its digital counterparts due to novel digital TDI implementation in terms of power consumption, noise and chip area. ROIC supports bi-directional scan, multiple gain settings, bypass operation, automatic gain adjustment, pixel select/deselect, and is programmable through serial or parallel interface. Input referred noise of ROIC is less than 750 rms electrons, while power consumption is less than 20mW. ROIC is designed to perform both in room and cryogenic temperatures.
This paper presents novel unit cell architecture for short wave infrared (SWIR) imaging applications. It has two input stages which are CTIA and SFD covering for both respectively low and high light levels and automatic input stage selection circuitry that chooses best input stage. A user can select 2 modes for FPA manual and automatic mode. In manual mode, user can set CTIA or SFD for all pixels according to user needs. In automatic mode, each pixel selects input stage itself according to light level. Automatic input stage selection for each pixel brings high SNR level and low noise along with highest possible dynamic range. Standard CMOS 0.18µm TSMC technology is used to realize unit cell. In the architecture of unit cell, circuit level techniques are used to optimize layout size.
Design and realization of a 144x7 silicon readout integrated circuit (ROIC) based on switched capacitor TDI for
MCT LWIR scanning type focal plane arrays (FPAs) and its corresponding hybrid integrated test circuits are
presented. TDI operation with 7 detectors improves the SNR of the system by a factor of √7, while oversampling
rate of 3 improves the spatial resolution of the system. ROIC supports bidirectional scan, 5 adjustable gain
settings, bypass operation, automatic gain adjustment in case of mulfunctioning pixels and pixel select/deselect
properties. Integration time of the system can be determined by the help of an external clock. Programming of
ROIC can be done in parallel or serial mode according to the needs of the system. All properties except pixel
select/deselect property can be performed in parallel mode, while pixel select/deselect property can be performed
only in serial mode. ROIC can handle up to 3.75V dynamic range with a load of 25pF and output settling time of
80ns. Input referred noise of the ROIC is less than 750 rms electrons, while the power consumption is less than
100mW. To test ROIC in absence of detector array, a process and temperature compensated current reference
array, which supplies uniform input current in range of 1-50nA to ROIC, is designed and measured both in room
and cryogenic (77ºK) temperatures. Standard deviations of current reference arrays are measured 3.26% for 1nA
and 0.99% for 50nA. ROIC and current reference array are fabricated seperately, and then flip-chip bonded for the
test of the system. Flip-chip bonded system including ROIC and current reference test array is successfully
measured both in room and cryogenic temperatures, and measurement results are presented. The manufacturing
technology is 0.35μm, double poly-Si, four metal, 5V CMOS process.
Design and measurement of a silicon readout integrated circuit (ROIC) based on switched capacitor time delay
integration (TDI) technique for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI)
functionality for scanning type of detector by using switched capacitor technique with a supersampling rate of
three, increasing SNR and the spatial resolution. ROIC, in terms of functionality, is capable of bidirectional scan,
programmable integration time, 5 gain settings at the input and auto gain adjustment with pixel deselection capability.
Programming can be done parallel or serially with test mode functionality. ROIC can handle up to 3.75V dynamic range
with the load being 25pF capacitive, output settling time is less than 80 nsec. This low power ROIC consumes less than
100mW. Moreover, input referred noise is less than 750 rms electrons. Simulations and measurements are done in both
room temperature and cryogenic (77 °K) temperatures. In order to measure and simulate chip without a detector, process
and temperature invariant current source block that imitate detector currents are designed as well. The manufacturing
technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process.
Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates
time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and
the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in
current domain by using switched current structures that reduces required area for chip and improves linearity
performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain
settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V
dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with
1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing
technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process.
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