There are two complementary requirements for implementing energy-harvested applications: the energy harvesting solution and the ultra-low power (ULP) requirements for the circuits. We address the ULP requirements by combining logically consistent design methodologies based on asynchronous streams to provide the essential blocks for a miniaturized ULP “mote.” First, we use an asynchronous stream data representation enabled by the use of continuous time Sigma-Delta modulators as analog-to-stream converters of sensor inputs. Second, we use Asynchronous Stream Processing (ASP) for ULP algorithms equivalent to DSP algorithms. Third we use Asynchronous Stochastic Computing (ASC) for ULP computations, including Machine applications such as Random Forest. Finally, we use Asynchronous Impulse Radio (AIR) UWB as a direct stream-to-radio mapping for compact wireless communication closes the loop for a ULP IoT mote from sensor input to wireless link.
Magnetic skyrmions are quasiparticle configurations in a magnetic film that can act as information carrying bits for ultrasmall, low power nonvolatile memory. Skyrmions can be nucleated and driven by spin-orbit torque from a current driven in a heavy metal underlying a ferromagnetic layer, the configuration commonly called a racetrack. Recently it has been shown that by hybridizing the skyrmion between Neel and Bloch types the magnus effect on skyrmion motion, which makes it veer from a straight path down a racetrack, can be effectively canceled which provides them a self-focused naturally converging lane" to travel through. This is achieved by exploiting the voltage controlled magnetic anisotropy effect whereby the magnetic anisotropy of the ferromagnetic racetrack can be positionally modulated by a gate voltage. In this work we show, using detailed micromagnetic simulations, that by using hybrid skyrmions we can obtain demultiplexer functionality out of a racetrack. We further propose a hybrid skyrmionic reconfigureable computing fabric. In conventional CMOS based field programmable gate arrays, SRAM cells are used to build a LUTs storing pre-computed truth-table of a Boolean function and a multiplexer selects one of the storage cells as the output. We show that non-volatile hybrid skyrmions can also act as the memory element and the gateable self-focused nature of the hybrid skyrmions can be exploited to program the proposed CMOS-skyrmion hybrid design to perform different logic operations. The low driving energy and non-volatility of magnetic skyrmion in a racetrack promises the development of energy efficient programmable architecture for future system-on-a-Chip (SoC) designs.
The end of Moore’s Law and the rise of “smart” consumer electronics has wide opened the gate for creative hardware design for the next few decades. While linear algebra accelerators and emulated hardware on FPGA has made some advances in this direction, a fundamentally different approach is required for reaching the efficiency and performance that will be necessary to embed cognitive computing in-situ in these next generation devices. To address this problem, in this work, we present a collection of spintronic hardware building blocks, fabricable with present day technology, that can be used to build biologically inspired neuromorphic hardware. These hardware units provide neuromorphic behavior derived from their physics and manifested in their electrical characteristics, therefore opening the pathway for compact, low power and VLSI grade scalability using these units. The collection contains two types of stochastic neuron (SN) devices: Analog (ASN) and Binary (BSN) as well as multi-level programmable synaptic connections that can be used for implementing compact dendrites. We discuss the area and power savings brought on by these building blocks and compared with an example design using FPGAs. This functionally complete but minimal set of neuromorphic building blocks can be used to implement a variety of neuromorphic architectures, as demonstrated in this work. We end the discussion with design ideas for neuromorphic architectures, which do not merely implement fast linear algebra but go beyond to elevate compact, physics-based field programmable neuromorphic arrays as first class citizens in every designers toolkit.
In this work we show how we can build a technology platform for cognitive imaging sensors using recent advances in recurrent neural network architectures and training methods inspired from biology. We demonstrate learning and processing tasks specific to imaging sensors, including enhancement of sensitivity and signal-to-noise ratio (SNR) purely through neural filtering beyond the fundamental limits sensor materials, and inferencing and spatio-temporal pattern recognition capabilities of these networks with applications in object detection, motion tracking and prediction. We then show designs of unit hardware cells built using complementary metal-oxide semiconductor (CMOS) and emerging materials technologies for ultra-compact and energy-efficient embedded neural processors for smart cameras.
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