Dr. Nishath Verghese Profile

Dr. Nishath Verghese

Vice President R&D Design Products at Cadence Design Systems Inc

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Publications (9)

Proceedings Article | 3 April 2010 Paper

Foundry verification of IP and incoming designs for manufacturing variability

Li-Fu Chang, Julia Fu, Josh Yang, Elain Zou, Philippe Hurat, Nishath Verghese, Hua Ding

Proceedings Volume 7641, 76410F (2010) https://doi.org/10.1117/12.848018

KEYWORDS: Lithography, Databases, Etching, Silicon, Diffusion, Design for manufacturing, Transistors, Optical proximity correction, Critical dimension metrology, Model-based design

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Proceedings Article | 11 March 2010 Open Access

Realizing a 45-nm system on chip in the age of variability

Laurent Le Cam, Andy Appleby, Philippe Hurat, Benoit Carpentier, Kuang-Han Chen, Nishath Verghese

Proceedings Volume 7641, 764106 (2010) https://doi.org/10.1117/12.848023

KEYWORDS: Semiconductors, Lithography, Databases, Metals, Manufacturing, Design for manufacturing, System on a chip, Model-based design, Chemical mechanical planarization, Design for manufacturability

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Proceedings Article | 13 March 2009 Paper

Variations in timing and leakage power of 45nm library cells due to lithography and stress effects

Kayvan Sadra, Mark Terry, Arjun Rajagopal, Robert Soper, Donald Kolarik, Tom Aton, Brian Hornung, Rajesh Khamankar, Philippe Hurat, Bala Kasthuri, Yajun Ran, Nishath Verghese

Proceedings Volume 7275, 72750K (2009) https://doi.org/10.1117/12.816485

KEYWORDS: Lithography, Logic, Statistical analysis, Capacitors, Data modeling, Computer simulations, Design for manufacturing, Transistors, Optical proximity correction, Convolution

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Proceedings Article | 13 March 2009 Paper

Layout electrical cooptimization for increased tolerance to process variations

Lionel Riviere-Cazaux, Philippe Hurat, Bala Kasthuri, Larry Layton, Nishath Verghese

Proceedings Volume 7275, 727506 (2009) https://doi.org/10.1117/12.813969

KEYWORDS: Lithography, Logic, Silicon, Reliability, Design for manufacturing, Photomasks, Transistors, Field effect transistors, Optimization (mathematics), Tolerancing

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Proceedings Article | 19 March 2008 Paper

Implementation of silicon-validated variability analysis and optimization for standard cell libraries

Raphael Bingert, Alain Aurand, Jean-Claude Marin, Eric Balossier, Thierry Devoivre, Yorick Trouiller, Florent Vautrin, Nishath Verghese, Richard Rouse, Michel Cote, Philippe Hurat

Proceedings Volume 6925, 69250M (2008) https://doi.org/10.1117/12.772897

KEYWORDS: Lithography, Data modeling, Etching, Silicon, Shape analysis, Transistors, Molybdenum, Model-based design, Device simulation, Instrument modeling

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Proceedings Article | 19 March 2008 Paper

Context analysis and validation of lithography induced systematic variations in 65nm designs

Arjun Rajagopal, Anand Rajaram, Raguram Damodaran, Frank Cano, Srinivas Swaminathan, Clive Bittlestone, Mark Terry, Mark Mason, Yajun Ran, Haizhou Chen, Robert Ritchie, Bala Kasthuri, Jac Condella, Philippe Hurat, Nishath Verghese

Proceedings Volume 6925, 69250A (2008) https://doi.org/10.1117/12.778836

KEYWORDS: Lithography, Data modeling, Etching, Silicon, Scanning electron microscopy, Transistors, Optical proximity correction, Critical dimension metrology, Model-based design, Process modeling

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Proceedings Article | 4 March 2008 Paper

Microprocessor chip timing analysis using extraction of simulated silicon-calibrated contours

Toshiaki Yanagihara, Takeshi Hamamoto, Koya Sato, Atsushi Okamura, Toshiyuki Matsunaga, Naohiro Kobayashi, Tatsuya Maekawa, Nishath Verghese, Jac Condella, Philippe Hurat

Proceedings Volume 6925, 69250O (2008) https://doi.org/10.1117/12.773013

KEYWORDS: Lithography, Clocks, Data modeling, Databases, Etching, Silicon, Shape analysis, Transistors, Optical proximity correction, Picosecond phenomena

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Proceedings Article | 21 March 2007 Paper

Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability

Darsun Tsien, Chien Kuo Wang, Yajun Ran, Philippe Hurat, Nishath Verghese

Proceedings Volume 6521, 65210F (2007) https://doi.org/10.1117/12.712281

KEYWORDS: Lithography, Silicon, Manufacturing, Resistance, Capacitance, Transistors, Optical proximity correction, Picosecond phenomena, Process modeling, Resolution enhancement technologies

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Proceedings Article | 21 March 2007 Paper

Model-based approach for design verification and co-optimization of catastrophic and parametric-related defects due to systematic manufacturing variations

Dan Perry, Mark Nakamoto, Nishath Verghese, Philippe Hurat, Rich Rouse

Proceedings Volume 6521, 65210E (2007) https://doi.org/10.1117/12.712471

KEYWORDS: Lithography, Data modeling, Metals, Silicon, Manufacturing, Design for manufacturing, Transistors, Model-based design, Instrument modeling, Design for manufacturability

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Model-based hotspot detection and silicon-aware parametric analysis help designers optimize their chips for yield, area and performance without the high cost of applying foundries' recommended design rules. This set of DFM/ recommended rules is primarily litho-driven, but cannot guarantee a manufacturable design without imposing overly restrictive design requirements. This rule-based methodology of making design decisions based on idealized polygons that no longer represent what is on silicon needs to be replaced. Using model-based simulation of the lithography, OPC, RET and etch effects, followed by electrical evaluation of the resulting shapes, leads to a more realistic and accurate analysis. This analysis can be used to evaluate intelligent design trade-offs and identify potential failures due to systematic manufacturing defects during the design phase. The successful DFM design methodology consists of three parts: 1. Achieve a more aggressive layout through limited usage of litho-related recommended design rules. A 10% to 15% area reduction is achieved by using more aggressive design rules. DFM/recommended design rules are used only if there is no impact on cell size. 2. Identify and fix hotspots using a model-based layout printability checker. Model-based litho and etch simulation are done at the cell level to identify hotspots. Violations of recommended rules may cause additional hotspots, which are then fixed. The resulting design is ready for step 3. 3. Improve timing accuracy with a process-aware parametric analysis tool for transistors and interconnect. Contours of diffusion, poly and metal layers are used for parametric analysis. In this paper, we show the results of this physical and electrical DFM methodology at Qualcomm. We describe how Qualcomm was able to develop more aggressive cell designs that yielded a 10% to 15% area reduction using this methodology. Model-based shape simulation was employed during library development to validate architecture choices and to optimize cell layout. At the physical verification stage, the shape simulator was run at full-chip level to identify and fix residual hotspots on interconnect layers, on poly or metal 1 due to interaction between adjacent cells, or on metal 1 due to interaction between routing (via and via cover) and cell geometry. To determine an appropriate electrical DFM solution, Qualcomm developed an experiment to examine various electrical effects. After reporting the silicon results of this experiment, which showed sizeable delay variations due to lithography-related systematic effects, we also explain how contours of diffusion, poly and metal can be used for silicon-aware parametric analysis of transistors and interconnect at the cell-, block- and chip-level.

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