Dr. Stéphane Larivière Profile

Dr. Stéphane Larivière

at imec

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Author

Publications (11)

Proceedings Article | 25 May 2022 Presentation + Paper

Patterning of Ru metal lines at 18nm pitch

Stefan Decoster, Souvik Kundu, Frédéric Lazzarino, Stéphane Larivière, Martin O'Toole, Gayle Murdoch, Quoc Toan Le, Marleen van der Veen, Nancy Heylen

Proceedings Volume 12056, 1205604 (2022) https://doi.org/10.1117/12.2614267

KEYWORDS: Metals, Ruthenium, Etching, Double patterning technology, Reactive ion etching

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Proceedings Article | 22 February 2021 Presentation

Electrical validation of massive E-beam defect metrology in EUV-patterned interconnects

Nicola Kissoon, Etienne De Poortere, David Hellin, Stefan Decoster, Gayle Murdoch, Stephane Lariviere, Elisabeth Camerotto, Sandip Halder, Philippe Leray, Malgorzata Jurczak, Guillaume Schelcher

Proceedings Volume 11611, 116110Q (2021) https://doi.org/10.1117/12.2584807

KEYWORDS: Metrology, Inspection, Ruthenium, Metals, Extreme ultraviolet, Etching, Electron beam lithography, Defect detection

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Proceedings Article | 16 October 2019 Presentation

Large area EUV via yield analysis for single damascene process: voltage contrast, CD and defect metrology (Conference Presentation)

Victor Blanco Carballo, Sara Paolillo, Marleen van der Veen, Stephane Lariviere, Gian Lorusso, Etienne de Poortere, Cyrus Tabery, Fu Qiao, shu-yu lai, marc kea, Luke wang, yu-chi Su, Joe Oh, jim huang, jimmy chen, jonathan huang

Proceedings Volume 11147, 111470B (2019) https://doi.org/10.1117/12.2536943

KEYWORDS: Inspection, Extreme ultraviolet, Metrology, Etching, Chemical mechanical planarization, Polishing, Logic, Optical alignment, Overlay metrology, Copper

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Proceedings Article | 26 March 2019 Paper

Process window discovery methodology for extreme ultraviolet (EUV) lithography

Sandip Halder, Dieter Van den Heuvel, Stephane Lariviere, Philippe Leray, Kaushik Sah, Andrew Cross, Antonio Mani

Proceedings Volume 10959, 109591V (2019) https://doi.org/10.1117/12.2515805

KEYWORDS: Stochastic processes, Inspection, Extreme ultraviolet, Modulation, Semiconducting wafers, Extreme ultraviolet lithography, Optical inspection, Critical dimension metrology, Bridges, Lithography

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Proceedings Article | 20 March 2019 Presentation + Paper

Virtual fabrication and advanced process control improve yield for SAQP process assessment with 16 nm half-pitch

Benjamin Vincent, S. Lariviere, C. Wilson, R. Kim, J. Ervin

Proceedings Volume 10963, 109630Q (2019) https://doi.org/10.1117/12.2518099

KEYWORDS: Optical lithography, 3D modeling, Critical dimension metrology, Process control, Semiconducting wafers, Etching, Yield improvement, Silicon

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Proceedings Article | 23 March 2018 Presentation + Paper

Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers

Stéphane Larivière, Christopher Wilson, Bogumila Kutrzeba Kotowska, Janko Versluijs, Stefan Decoster, Ming Mao, Marleen van der Veen, Nicolas Jourdan, Zaid El-Mekki, Nancy Heylen, Els Kesters, Patrick Verdonck, Christophe Béral, Dieter Van den Heuvel, Peter De Bisschop, Joost Bekaert, Victor Blanco, Ivan Ciofi, Danny Wan, Basoene Briggs, Arindam Mallik, Eric Hendrickx, Ryoung-han Kim, Greg McIntyre, Kurt Ronse, Jürgen Bömmels, Zsolt Tőkei, Dan Mocuta

Proceedings Volume 10583, 105830U (2018) https://doi.org/10.1117/12.2299389

KEYWORDS: Extreme ultraviolet, Optical lithography, Etching, Tin, Resistance, Metals, Semiconducting wafers, Critical dimension metrology, Photomasks, Copper

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Proceedings Article | 16 October 2017 Presentation

EUV single patterning for logic metal layers: achievement and challenge (Conference Presentation)

Ryoung-Han Kim, Werner Gillijns, Youssef Drissi, Jae Uk Lee, Darko Trivkovic, Victor Blanco Carballo, Stephane Larivière, Rudi De Ruyter, Morin Dehan, Gregory McIntyre, Ling Ee Tan

Proceedings Volume 10450, 1045004 (2017) https://doi.org/10.1117/12.2281738

KEYWORDS: Photomasks, Extreme ultraviolet, Optical lithography, Logic, Optical proximity correction, SRAF, Data conversion, Metals, Manufacturing, Semiconducting wafers

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Proceedings Article | 26 April 2017 Presentation + Paper

Design and pitch scaling for affordable node transition and EUV insertion scenario

Ryoung-han Kim, Julien Ryckaert, Praveen Raghavan, Yasser Sherazi, Peter Debacker, Darko Trivkovic, Werner Gillijns, Ling Ee Tan, Youssef Drissi, Victor Blanco, Joost Bekaert, Ming Mao, Stephane Larivière, Greg McIntyre

Proceedings Volume 10148, 101480V (2017) https://doi.org/10.1117/12.2257885

KEYWORDS: Photomasks, Logic, Etching, SRAF, Extreme ultraviolet, Optical lithography, Metals, Computational lithography, Optical proximity correction, Semiconductor manufacturing

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Proceedings Article | 24 March 2017 Presentation + Paper

SAQP and EUV block patterning of BEOL metal layers on IMEC's iN7 platform

Joost Bekaert, Paolo Di Lorenzo, Ming Mao, Stefan Decoster, Stéphane Larivière, Joern-Holger Franke, Victor M. Blanco Carballo, Bogumila Kutrzeba Kotowska, Frederic Lazzarino, Emily Gallagher, Eric Hendrickx, Philippe Leray, R. Ryoung-han Kim, Greg McIntyre, Paul Colsters, Friso Wittebrood, Joep van Dijk, Mark Maslow, Vadim Timoshkov, Ton Kiers

Proceedings Volume 10143, 101430H (2017) https://doi.org/10.1117/12.2258004

KEYWORDS: Optical lithography, Extreme ultraviolet, Back end of line, Metals, Logic, Extreme ultraviolet lithography, Etching, Double patterning technology, Lithography, Photomasks, Stochastic processes, System on a chip, Semiconducting wafers, Critical dimension metrology

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Proceedings Article | 24 March 2017 Presentation + Paper

Single exposure EUV patterning of BEOL metal layers on the IMEC iN7 platform

V. Blanco Carballo, J. Bekaert, M. Mao, B. Kutrzeba Kotowska, S. Larivière, I. Ciofi, R. Baert, R. H. Kim, E. Gallagher, E. Hendrickx, L. E. Tan, W. Gillijns, D. Trivkovic, P. Leray, S. Halder, M. Gallagher, F. Lazzarino, S. Paolillo, D. Wan, A. Mallik, Y. Sherazi, G. McIntyre, M. Dusa, P. Rusu, T. Hollink, T. Fliervoet, F. Wittebrood

Proceedings Volume 10143, 1014318 (2017) https://doi.org/10.1117/12.2258005

KEYWORDS: Metals, Extreme ultraviolet lithography, Optical lithography, Back end of line, Extreme ultraviolet, Etching, Semiconducting wafers, Logic, Critical dimension metrology, Tin

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Proceedings Article | 21 March 2017 Presentation + Paper

Co-optimization of lithographic and patterning processes for improved EPE performance

Mark Maslow, Vadim Timoshkov, Ton Kiers, Tae Kwon Jee, Peter de Loijer, Shinya Morikita, Marc Demand, Andrew Metz, Soichiro Okada, Kaushik Kumar, Serge Biesemans, Hidetami Yaegashi, Paolo Di Lorenzo, Joost Bekaert, Ming Mao, Christophe Beral, Stephane Larivière

Proceedings Volume 10149, 101490N (2017) https://doi.org/10.1117/12.2257979

KEYWORDS: Semiconducting wafers, Photoresist processing, Source mask optimization, Overlay metrology

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Complimentary lithography is already being used for advanced logic patterns. The tight pitches for 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns are made using EUV exposures. At the same time, control requirements of CDU, pattern shift and pitch-walk are approaching sub-nanometer levels to meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Local CDU, and Local Placement Error (LPE), are dominant factors in the total Edge Placement error budget. In the lithography process, improving the imaging contrast when printing the core pattern has been shown to improve the local variability. In the etch process, it has been shown that the fusion of atomic level etching and deposition can also improve these local variations. Co-optimization of lithography and etch processing is expected to further improve the performance over individual optimizations alone.

To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.

Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.

Showing 5 of 11 publications

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