With the improvement of chip debugging technology performance, the chip physical attack technology has also been developed rapidly. At present, the active shield has become the main protection against physical attacks on the chip. In this paper, for the shortcomings of digital shield detection circuit which cannot resist rewiring attack, we propose a scheme to collect some channel signal propagation delay to detect whether the shield is under rewiring attack on the basis of random code stream detection circuit. The scheme is applicable to parallel multi-channel shields. Random sequences is passed to the inner channels and pulse signals is passed to the outer channels, and the random sequence is compared in the detection circuit to determine whether the random sequence is consistent and the pulse signal width is within the error range, so as to determine whether the shield is damaged or modified. The final experiment shows that the scheme has the characteristics of simple digital type detection circuit, low overhead, after the implementation in smic0.18um process, the area of 25766um2, power consumption of 1.6639mw, can identify more than 8% of the shield failure area of rewiring attacks, to make up for the inherent parametric type detection circuit complexity defects.
When compressing massive data, using software implementation of Zstandard (Zstd) algorithm will occupy a lot of processor resources, and it will lead to performance bottleneck due to serial data dependency, hardware acceleration of Zstd algorithm is an effective solution to the above problems. Therefore, in this paper, we propose a hardware architecture for concurrent streaming of multiple hash tables applicable to the Zstd algorithm. Using this design scheme, the RTL-based VCS simulation verification shows that the compression ratio almost reaches the standard of software, the compression speed of hardware is about 5.5 times of software compression speed, and the decompression speed of hardware is about 5 times of software, where the compression speed reaches up to 1.17GB/s and decompression speed reaches up to 1.89GB/s, and compared with the existing hardware implementation of Zstd, the compression speed is about 11.4% higher than that of the existing hardware implementation of Zstd.
SRAM PUF is already embedded in MCU as a traditional memory, it can be used as a PUF module without hardware modification and additional hardware overhead. However, due to different working environments such as temperature and voltage, the response sequence generated by SRAM PUF is not necessarily the same for the same excitation. Therefore, the resulting response sequence needs to be processed to get a unique stable key. In this paper, a soft decision fuzzy extractor scheme based on RM cascade code is proposed, and the simulation verification and reliability test are carried out by using the system simulation platform, and the final results show that the error rate is below 0.08, the reliability reaches more than 0.999999, the required SRAM number is reduced to 2464, which is reduced by 47.57% compared with the traditional hard judgment [12], and the consistency index can reach 99.99 in the temperature range of 20℃~80℃.
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