This PDF file contains the front matter associated with SPIE Proceedings Volume 12052, including the Title Page, Copyright information, Table of Contents, and Conference Committee listings.

Spin Orbit Torque (SOT) magnetic random-access memory (MRAM) offers the possibility to realize non-volatile ultra-high-speed technology. SOT-MRAM can also potentially reduce embedded memory footprint, which would inturn reduce silicon cost. However, there are certain challenges to overcome for SOT integration with logic. SOTMRAM needs a tall ‘VIA’ for the MTJ connection to the transistor. The height of this tall ‘VIA’ can vary from 60nm to 300nm for the N5 technology node. The VIA Critical Dimension (CD) depends upon metal width (30nm) which connects MTJ to read transistor. Thus, the aspect ratio needed for proper SOT integration is at least 10. This high aspect ratio is a major challenge for SOT integration, but it can be reduced (even down to 2) at the cost of SOT and MTJ stack integration complexity. On the other hand, keeping WL spacing constant and reducing WL width to facilitate increased MTJ connecting metal width (hence improve the AR for the same height) will increase the WL resistance. This WL resistance increment degrades WL delay as parasitic resistance is more problematic than capacitance at advanced nodes. In conclusion, while a tall VIA for SOT-MRAM has integration challenges due to the high VIA aspect ratio, mitigating this by means of wider VIA CD can potentially increase WL delay. Therefore, a comprehensive DTCO considering different bit-cells, SOT integration options and Memory performance is needed for SOT technology to be adopted at the most advanced technology nodes.

In semiconductor manufacturing, yield and cost are important factors to predict and improve the productivity of manufactures. A yield prediction model and the corresponding cost of the ownership with advanced technology nodes beyond imec 5nm are proposed in this paper. In this study, the compact die yield data and the cost will be compared between imec 8nm, 7nm and 5nm technology nodes. With technology nodes scaling, the node-to-node scalability can be impacted by the process complexity, different number of layers, and chip size, etc. With proper process parameters, the yield per layer and the yield per chip can be extracted. In addition, the productivity and turn-around-time (TAT), also called cycle time (CT), can also be calculated based on yield and cost model with complex manufacturing process steps to improve the manufacturability and turnaround-time (TAT). The productivity can be easily evaluated by the yield prediction model since productivity and yield are inseparable in manufacturing. Based on the process assumption, the turn-around-time (TAT) can be precisely estimated by the result of the wafer process time including the time of each step provided by the imec database. As the scaling persists, growing complexity in semiconductor manufacturing gives rise to a concern on the yield and cost. We studied a yield model and the corresponding cost of the ownership for imec technology nodes to discuss their manufacturability. With technology nodes progression, the node-to-node scalability is shown to be impacted by the process complexity from the number of layers, patterning methods and chip size, etc. In addition, productivity and turn-aroundtime (TAT), also referred as the cycle time (CT), can also be estimated to be used as an important parameter to enhance productivity and optimize profitability in semiconductor manufacturing.

This paper presents a new transistor design that enables scalability of a nanosheet field effect transistor (FET) architecture. By introducing an innovative patterning design for the nanosheets (a zigzag shape), the contacted poly pitch (CPP) can be reduced to a 30nm size. Semiconductor virtual fabrication was used to create virtual prototypes of this new device architecture and evaluate different process and design assumptions.

Tuning the spectrum of a scanner’s excimer laser light source is a well-known technique to achieve improved depth of focus (DOF) for an exposure. Previous studies have focused on the imaging improvement capabilities of readily available spectral shapes such as Gaussian E95 single peak width, as well as dual-peak spectral shapes where the spacing of the peaks can be varied. It is commonly known that adjustments in the laser spectrum must be carefully considered since exposure latitude (EL) can also be reduced as DOF is increased. By carefully engineering the laser’s spectrum, DOF can be maximized with very little impact to exposure latitude. Undesirable speckle contrast can also be reduced as laser bandwidth is increased. Traditionally, these approaches have been used to improve DOF of thick resist applications such as CMOS image sensors. Other areas such as NAND Flash have introduced laser spectrum engineering (SE) to compensate for topography effects between periphery and array regions. Recently, advances in laser hardware have enabled new and unique spectral shapes to be used for imaging. In this paper, we explore the various spectral profiles possible on the latest Gigaphoton GT66A ArFi light sources. New applications of these spectrum shapes are considered for foundry logic-type levels. First, a representative 14nm-node logic layer is considered. Source Mask Optimization (SMO) is performed while various widths of spectral profiles are used as input, such as traditional E95 Gaussian profiles, dual-peak, and flat top. By accounting for the laser spectrum during SMO, common DOF can be improved by ≥ 20% without a noticeable decrease in exposure latitude. The SMO sources and optimized masks are also different from each other and the nominal cases, depending on the spectral distribution used. Next, we explore simultaneously optimizing the laser spectrum, source, and mask in an experimental SMO+SE. Spectra can be constrained to keep symmetric profiles about the 193nm center point. Improved lithographic performance can result from the application of programmable laser spectra combined with pixelated sources and inverse lithography (ILT).

Emerging AI and 5G applications such as connected devices, autonomous vehicles, virtual/augmented reality, and clouds are driving beyond traditional pitch scaling. Wired and wireless infrastructure devices are accelerating their migration towards leading-edge technologies in order to achieve higher performance, better power efficiency, and improved functionality, which leads unprecedented demand for compute power in datacenters and communication infrastructures. In addition, high-speed interfaces are supporting faster data throughput and improved connectivity. But the area scaling and performance improvement of semiconductors are getting harder every year and numerous technologies are suggested to overcome these limitations. In this presentation we aim to provide an overview of the requirements, outline some of the key design parameters and provide a few examples of contemporary soluions beyond traditional Moore’s-Law scaling for the insatiable compute demand.

Computational Lithography has come a long way since its inception in the mid-nineties. The problem it solves is both fundamental and difficult, and if one believes in the continuation of Moore’s Law, one can only conclude that this problem is going to become exponentially more challenging. With the relentless march of technology nodes, we have had to squeeze increasingly complex Physics into a limiting compute envelope; several assumptions that were made thus far to arrive at practical computational lithography solutions might soon become invalid. To keep pace with this increasing complexity, computational lithography must change. An obvious path to the next generation of computational lithography solutions is to take advantage of the awesome capabilities of modern GPUs. To do this optimally, we believe, one must reimagine and rearchitect the basic algorithms of computational lithography. This talk will provide both a historic context to this evolution, as well as a glimpse into NVIDIA’s efforts and collaborations to enable next generation computational lithography for the semiconductor industry at large.

Ultraviolet nanoimprint lithography (NIL) is a simple contact process that is attractive and promising process for high pattern fidelity, without blurring effect due to light scattering or acid diffusion in the resist. Specifically, complicated 3D patterns, fine 2D patterns, and fine 1D patterns can be formed in fewer process steps compared to those for optical lithography. On the other hand, there are fewer adjustment knobs for process tuning in NIL; therefore, it is necessary to introduce design restrictions customized for NIL to improve the process margin. Since pattern transfer is performed through filling of a resist having a finite volume, a design constraint considering filling property is required to reduce defect density and improve throughput. In this study, two types of design constraints are examined to address the NIL process margin problem. One is a NIL alignment mark design that satisfies both signal strength and filling characteristics. The other is a combination of the pattern coverage rule with wafer topography that achieves good filling characteristics under various substrate unevenness conditions. Experiment results were interpolated with NIL process simulations and common areas under various conditions were extracted to identify the design rules for achieving large process margins. By using a design flow that considers these rules, we believe that high volume manufacturing (HVM) yields can be increased considerably by reducing yield issues and reducing redesign loops.

With increasing process complexity, quantifying impact of process parameters on scaling performance is of utmost importance. Edge placement error (EPE) budget is a key limiter for scaling. We present a Machine learning based analytics framework to perform impact analysis of various process assumptions on EPE. This would help us identify in advance the process bottlenecks for emerging nodes. For imec N3 process, one key challenge is via to buried power rail overlap which is shown to have a dependence on 15 process parameters. We first generate an exhaustive dataset of overlap EPE errors with respect to process assumptions using Monte Carlo simulation. Then a neural network model was built to model EPE error for given process parameters. Our engine ranked imec N3 litho process priorities using sensitivity analysis and identified key process bottlenecks. An impact analysis was performed to demonstrate 18% improvement in overlap edge placement error. This methodology can be used to guide the community about direction of early technology path-finding to optimize device performance.

Curvilinear design layout is becoming increasingly prevalent in semiconductor manufacturing industry. One of the applications is Silicon Photonics. Silicon Photonics design layout requires the use of curvilinear shapes to minimize the loss of signal strength. Other applications include curvilinear Mask Proximity Correction (CL MPC), verification (CL MPCV), Mask Rule Checking (CL MRC), microelectromechanical system (MEMS), on-chip metasurface optics, etc. Curvilinear design layout poses new challenges to computational lithography tools that were developed mainly to handle Manhattan geometries. It has been found that the geometry-based error classification used in the Optical Proximity Correction (OPC) verification flow has its limitations to support curvilinear designs. In this paper, we present our innovative work of using Siemens EDA Calibre® OPCVerify Machine Learning (ML) Classify technology to classify error markers in the feature vector space instead of traditional pattern’s vertices and edges geometries. There are five steps in our OPCVerify ML Classify: 1. use primary checks to output error markers, 2. design features and create feature vector kernels, 3. collect feature vectors at error marker locations, 4. prepare patterns with pre-knowledge of desired classify guidance and train ML model, and 5. apply ML classify model to classify error markers on full layout in the feature vector space. In our experiments, ML Classify is successful in classifying OPC verification error markers in curvilinear designs. A drawn silicon photonics layout with 837,072 raw error locations has demonstrated our ML Classify tool’s capability to reduce the unique class count from 221,085 based on conventional geometry-based classify approach down to 51. We also developed further sub-classify feature which provides options to further sub-classify results by edge types, convex, concave, or straight line, and by polygon’s internal width and external space to neighboring polygons. The 51 unique class count becomes 2493 after the further sub-classify process. This methodology is not only good for silicon photonics application, but also good for other curvilinear photomask applications, like CL MPCV, MEMS, on-chip metasurface optics, and in general even Manhattan designs.

NAND flash memory is widely used as the primary storage medium with the development of IT technology. In order to increase the memory density and reduce cost per bit, Vertical-NAND (VNAND) technology has attracted attention. In VNAND technology, the cell array is formed in a vertical direction by stacking the multiple multi oxide/nitride layer deposition (MOLD) layer. As the number of stacked layer (Word-Line) is increased, however, several technical issues have been encountered such as miss-alignment between stacked layers, which is caused by MOLD shrinkage in memory process like etching and anneal. The mis-alignment leads to the bridge between word-line cut (WL-CUT) and channel hole (Ch. Hole), it causes a major failure in cell region. In present study, we proposed a novel automated system called Progressive Mis-Align Correction system (PMAC), which compensates for the systematic defect caused by misalignment between stacked layers. We also introduced a modelling method to estimate the degree of mis-align in unsampled regions using Random forest machine learning algorithm. In order to evaluate the performance, we applied the PMAC system to WL-CUT layer of 170-layer NAND product. We compared the turnaround time (TAT) and accuracy of PMAC system and the way of manual correction. We confirmed that the proposed system using a tool that has correction technology for each shape effectively reduced the turnaround time by up to 90% (14d to 2d) and the error of correction by up to 0.3nm. These results suggest that the PMAC system could improve the productivity.

The throughput of extreme ultraviolet lithography (EUVL) is a key factor in the cost of ownership of EUVL patterning at advanced nodes, and low dose exposure is a direct way to increase the wafer throughput. However, low dose exposure typically leads to poor CD uniformity and line-width roughness. In the paper, we investigate low dose EUV exposure via design and mask optimization, and experimentally show the methodology to achieve low dose EUV exposure while maintaining the process performance. The impact of mask CD bias, mask stack and the tonality on the exposure dose and the process performance will be discussed, together with the design retarget and OPC strategy.

According to the Power-Performance-Area requirements in advanced technology node, we already scaled down poly pitch (CPP) and metal pitch (MP) which considered as main factors to form standard cell (SDC) area. However, in recent technology nodes, the scaling of CPP and MP started to slow down, due to the physical limitation. To continue to meet the requirements, combined with Design-Technology co-optimization (DTCO), the height of standard cell would become the main factor here, which we could reduce it by reducing the number of tracks. In this paper, we would introduce 3DIC as one of the design options for 2nm node to keep scaling by reducing the cell height with its specific 3D structure and inserted booster. Also, we would introduce the coming challenges as importing 3D-IC to 2nm technology node.

We explore in this study imaging performance of horizontally oriented logic metal layer designs computationally, focusing on metal patterns with a pitch of 20nm (P20) and a tip-to-tip (T2T) range of 8- 35nm using 0.55 NA EUV single exposure. Simulations are performed by the method of source-mask optimization (SMO) using the Tachyon^TM software. The key assessed imaging parameters include the (normalized) image log-slope (NILS/ILS), overlapping depth of focus (DOF), and best focus (BF) shift. Simulation results show that traditional TaBN masks offer a reasonable overall contrast and DOF of both dense lines and through-pitch line patterns. Low-n masks offer benefits in contrast and dose. Low-n masks also show improvement in BF shift range, but such benefits vary with the extinction coefficient k as well as the pitch range and pattern selections. Other resolution enhancement techniques such as subresolution assistant features (SRAF) and bright-field imaging associated with metal-oxide-resists (MOR) also provide help to improve patterning performance. Metal designs with thick power rails have an impact on the contrast of neighboring patterns. Inner SRAF OPC and narrow power rails can effectively eliminate this impact. Patternable T2T size is type-dependent. Our study finds a flat ILS when T2T size is ≥15nm (for P20 lines) and a quick ILS drop when T2T size is < 15nm. It also reveals that complex T2T designs (e.g. staggered T2Ts) have lower contrasts. Additional care is needed in OPC other than avoiding such patterns in design. Our study confirms the potential replacement of 0.33 NA 3- to 4-time multipatterning by 0.55 NA single patterning.

Source mask optimization (SMO) is one of the most widely employed techniques at 7nm technology nodes. As new lithography techniques develop, lithography metrics of SMO used in cost functions (CF) are also developing quickly. Besides the standard critical dimension (CD) and edge placement error metrics, image log-slope (ILS) and ILS-DOF are also significant, which are penalties in SMO CF. A novel contrast-aware SMO is proposed in this paper to improve ILS in current edge placement error (EPE) based SMO flow. The target ILS, an appropriate penalty weight and the cutlines which should be applied the specific process window metric should be adjusted in several SMO iterations. The corresponding mask optimization results based on the qualified SMO model may provide a qualified retargeting strategy at the same time.

For 28 nm node semiconductor devices and beyond, more aggressive resolution enhancement techniques (RETs) such as sub-resolution assist features (SRAF), litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning(SAQP), and source-mask optimization (SMO) are utilized for the low k1 factor lithography processes. The litho-to-etch pattern fidelity is extremely critical since a slight lithography pattern weakness (ex: photoresist (PR) thickness loss, profile roughness ...) may be worsened after etch process due to the pattern loading effect, which will then induce physical defects that affect the final electrical performance. Rigorous lithography simulation can provide a reference of pattern weaknesses to modify mask layouts; but it is incapable of full-field mask data preparation. The post-etch critical dimensions (CDs) with a high accuracy optical proximity correction (OPC) model has become an important component; but it requires massive wafer data of post-litho and post-etch CDs, and will increase the runtime of the OPC flow for OPC modelers. In our previous submission [1-2], we had brought forth an algorithm that utilizes multi-intensity levels from conventional aerial image simulations to assess the physical profile through lithography to etch steps, and proposed a novel litho-etch correction method without suffering the lithography process window of SADP process. In this paper, we have improved this methodology and introduced a new approach of virtual etch target (VET) with virtual etch target threshold to assess post-etch CDs for various applications of memory patterning (dense features by SADP or SAQP process) and logic patterning (random features of lines, trenches and holes) more efficiently. The results not only matched post-etch wafer data, but also agreed with post-etch process window. Furthermore, this methodology can be utilized in generic OPC and post-OPC verification procedures to improve final pattern fidelity for logic and memory products.

Source Mask Optimization (SMO), which enables complex design geometries and improves lithography process window, is a key technology utilized in our hard disk drive (HDD) manufacturing. In this co-optimization technique, mask optimization has been extensively explored and well established in our community. However, source optimization of equal importance receives less attention even with a long history of development since 90s. In the source optimization, the light intensity from a source is generally perceived as a linear addition of intensity from each point source based on Abbe’s method. The drawback on this common approach is that the computation is intensive and timeconsuming as it involves the convolution between the pupil function modulated by each point source and the input mask. Here we present an algorithm of calculating transmission cross coefficients (TCC) for each point source in an illumination source. By following the Hopkins’s approach, the source TCC matrix can be interpreted as the summation of individual TCCs of point sources. Compared to the Abbe’s source formulation, the proposed algorithm provides a simpler, faster and accurate source representation, which is believed to be beneficial to the source mask optimization.

This work is evaluating Machine Learning (ML) architecture options for weak point detection methods embedded in Design for Manufacturing (DFM) signoff tools. As Deep Learning based models have been released into the customer design enablement space, we are investigating the tradeoffs between model simplicity, run time and prediction accuracy. With simpler model architectures, additional options for data augmentation become available that can potentially result in better model accuracy. For example, noise introduction in the training data set can help prevent overfitting and thus results in better model accuracy.

Design rules are geometric constraints imposed on IC layout to ensure products can be manufactured at an acceptable yield. Designs are required to pass sign-off design rule check (DRC) before tape-out. Foundries rely on DRC to ensure designs they accept are manufacturable. DRC runsets must be accurate, complete, and reliable. DRC runset qualification is critical in technology node deployment and maturation. The number, complexity and variation of design rules grow dramatically with advancing technology nodes. This increases the QA challenge to ensure quality and accuracy of runsets and their interdependent rule operations. Traditional methods of migrating previous node QA patterns, manually crafting new testcases, and targeted-pattern generation leave gaps in advanced process node qualification coverage. We deploy a novel synthetic layout generation approach to produce large varieties of complex layouts with high design space coverage to thoroughly qualify runsets, make runset improvements and release quality PDKs. We employ guided random Monte Carlo layout generation with user-defined layout construction rules. User-defined rules inform DRC requirements and assign weighted priorities to guide layout design styles. We generate stress DR layouts and high pattern coverage, with DRC-clean patterns and with deliberate DRC violations, to validate expected DRC results and exercise entire rule decks. In this paper, we show how Synthetic Layout Generation is integrated into runset QA flows, automatically generating stress DR conditions that manual efforts often miss, expand layout pattern space coverage, and improve runset execution coverage leading to higher quality on-time PDK development, qualification, and release.

Diversity of known hotspot patterns is important for hotspot detection and correction. Deliberate synthesis of hotspot patterns can improve such diversity. Machine learning generative network is a popular tool for image synthesis, but it should be trained with known hotspots anyway. We propose U-net hotspot generator. A key is to train the generator with CNN hotspot probability model, i.e. the generator is trained such that output is a variant of input image with high hotspot probability. The method allows any patterns, even coldspots, to be provided to the generator, which then yields their hotspot variants. Efficiency of hotspot generator is demonstrated through experiments.

In this paper, we are presenting a smart and efficient methodology to select the most representative patterns on the wafer. Calibre-SONR is doing Smart down-sampling to patterns on the wafer based on their features and choose the most representative ones to be used in different applications. In addition, it gives the user the flexibility to choose the range of needed representative patterns to tune their models on. A comparison between SONR down-sampling and typical offthe- shelf down-sampling and clustering techniques is done. SONR gives better coverage to the unique patterns than other techniques and able to handle larger data sets.

This paper demonstrates a new approach for hotspot detection in large design spaces. We present a new pattern matching technique, which is a multi-window pattern search that is deployed in a dynamic and precise way to search for similar patterns. Based on the matched locations the flow extracts and combines silicon awareness features and design level features to build comprehensive feature matrix that can be used in subsequent analytical analysis. The paper also shows the advantage of using this flow with respect to precise capture of hotspot and ~10X improvement on turnaround time for feature extraction compared with traditional methods. The output of this flow also facilitates and improves the data preparation process for machine learning model building.

As complex NTD resist behavior significantly impacts AF wafer printing , there is a need to better model NTD AF printing. We present our work to further enhance NTD compact modeling accuracy for AF printing prediction by physics-based and data-based methods. The physics-based enhancements are derived from improvements in behavioral mechanisms in exposed and partially exposed NTD materials. The data-based enhancements are derived from learning methodologies developed for predicting lithography hot-spots at the limits of process control. Both types of enhancements are needed to predict fine changes in imaging and resist behavior where traditional compact models break down.

A multi-objective optimization flow is developed to identify balanced compact optical proximity correction (OPC) models with ideal calibration accuracy, runtime performance and prediction accuracy. We demonstrate a model selection process based on Pareto front optimization to meet multiple modeling requirements in a single optimization step. A genetic search algorithm determines the final population that offers the best trade-off in set model properties. As a demonstration, we cooptimize calibration accuracy, verification accuracy and term count in a mode developed for hot spot prediction for a line and space memory layer. The optimization determines the minimum number of model terms to meet the off-nominal dose and focus patterning accuracy requirements in verification. Multi-objective optimization provides better verification process window condition (PWC) accuracy because of the multi-objective trade-off built into the genetic algorithm (GA). The optimizer also provides better calibration accuracy (Rms Weighted) than compact models with a fixed configuration because model composition is optimized during GA search. The resulting champion model is 30% more predictive and 5% faster in simulation using this approach. Results for a negative tone develop hole layer with a model complexity of up to 44 terms are also analyzed based on nominal only measurement data. We further show the models selected by multi-objective optimization have a lesser tendency to over-fit the calibration data. The methodology can be applied to streamline complex models for optimum performance and target error rate. In many cases, for smaller data sets, we show that simplified models provide improved verification accuracy within metrology error limits.

In photolithography, we need accurate models as computation engine for optical proximity correction (OPC). Traditional OPC modeling consists of a series of components for photo mask, optical exposure system, and resist materials. These models are trained using compact model forms based on wafer-level critical dimension (CD) or edge placement error (EPE) measurements. In recent years, advancements in neural networks and machine learning have had significant advancements. In this work, we evaluated advanced neural network-based resist models on a Tensor Flow machine learning platform. This work describes resist and optical response of machine learning (ML) model through process window to achieve improved model representation of lithography process. Using ML OPC vias mask as an example, we will show improved accuracy through dose and focus process conditions and verify model accuracy with physical hardware data. Also, we will compare multiple neural network-based modeling approaches, investigate the ML models’ impacts on OPC correction and verification recipes, and dataprep runtime. The machine learning based OPC with ML model and best practice will be implemented in cloud production environment.

MB-OPC contains a fragmentation step, in which each polygon edge is divided into a number of segments. Simple empirical rules dictate how the edges should be divided. Fragmentation strongly affects MB-OPC in its quality and runtime since OPC correction is performed segment by segment. Refragmentation using random forest classifier (RFC) is proposed. A segment and its surroundings are modeled using a number of features, which drive RFC to decide whether a segment should be further divided or not. It complements rule-based fragmentation in that small number of critical segments, which are not short enough and cause longer MB-OPC iterations, are quickly identified. When refragmentation is applied in standard rule-based fragmentation and MB-OPC flow, maximum EPE is reduced substantially (from 3.8nm to 2.4nm) with very marginal increase in the number of segments (7k to 7,093), yet OPC iterations are reduced (10 down to 8).

Data augmentation is a powerful technique in deep learning to increase the number of training data by using limited original data. We apply this technique to EUV lithography simulation based on convolutional neural network (CNN). In previous work, we developed a prototype CNN which reproduces the results of the rigorous electromagnetic (EM) simulations in a small mask area. The prediction time of CNN was 5,000 times faster than the calculation time of EM simulation. We trained the CNN by using 200,000 data which were the results of EM simulation. Although the prediction time of CNN was very short, it took a long time to build a huge amount of the training data. Especially when we enlarge the mask area the calculation time to prepare the training data becomes unacceptably long. The EM calculation time for 1,024 nm X 1,024 nm mask area takes 162 s. It will take a year to calculate 200,000 mask patterns. The training data of our CNN is the diffraction amplitudes of mask patterns. Assuming a periodic boundary condition, the diffraction amplitudes of the shifted or flipped mask pattern can be easily calculated by using the diffraction amplitudes of the original mask pattern. We apply this data augmentation technique to reduce the data preparation time for 1,024 nm X 1,024 nm mask area by a factor of 200. The accuracy of CNN is verified by comparing the CNN predictions with the results of EM simulation. Our CNN successfully reproduces critical dimensions and edge placement errors of line and space patterns.

As an advanced form of optical proximity correction (OPC), Inverse Lithography Technology (ILT) calculates the desired shapes on a photomask in free-form curvilinear types. It has become one of the key computational lithography solutions for advanced technology nodes, which may enable the most challenging features in IC designs and produce mask output that results in better process latitude and CD control on wafer than the one using conventional OPC [1]. Although curvilinear ILT technology has taken root in limited cases such as in hot spot repairment and in memory [2], it still experiences difficulties to be adopted as a full-chip solution due to its long computation time and consistency issues. In this paper, we will leverage Siemens pxOPC and introduce a fast full-chip curvilinear ILT mask generation flow with Mentor Graphics Calibre SONR, a Machine Learning (ML) method [3]. Siemens pxOPC TM is pixel-based optimization product designed to maximize lithography quality in terms of EPE, Common Process Window, ILS/NILS, MEEF, etc. It uses image gradient to indicate the mask movement and minimize the gradient magnitude to achieve the final mask. Calibre SONR is a product built upon Mentor’s Machine Learning Platform (MLP) combining multiple related applications under one license. It uses feature vectors which are shown to correlate well with design and fab printing behavior. SONR implements fuzzy Pattern Matching (PM) in feature vector space, which is different from traditional PM (either exact or fuzzy) in topological space. For the case of pattern reduction, traditional fuzzy PM selects patterns which are close geometrically to a reference pattern, while SONR make further pattern reduction without loss in pattern coverage since different topological patterns may share similar feature vectors. In this paper, we build a flow to use SONR to analyze patterns across the full chip and make corresponding selections for the final pxOPC solutions. With comparable wafer performance, our preliminary results show that the flow may exceed the existing best practice in terms of runtime reduction, enhanced full-chip consistency, and robust full-chip run. Figure 1 shows that the run time is improved by 60%. This paper is organized as follows. pxOPC is introduced in Section I. Our proposed SONR pattern reduction flow is described in Section II, followed by the fast full-chip curvilinear mask generation flow in Section III. Then Section IV provides simulation results and discussion in Section IV. Section V conclusions the paper. Keyword: Curvilinear, ILT, pxOPC, mask, machine learning, pattern selection, layout reduction REFERENCES [1] Le Hong, Fan Jiang, Alexander Tritchkov, James Word, Dan Zhang, “Inverse Lithography Recipe Optimization Using Genetic Algorithm”, SPIE 105871H (2018). [2] Linyong (Leo) Pang, P. Jeffrey Ungar, Ali Bouaricha , Lu Sha, Michael Pomerantsev, Mariusz Niewczas, Kechang Wang, Bo Su, Ryan Pearman, and Aki Fujimura "TrueMask ILT MWCO: full-chip curvilinear ILT in a day and full mask multi-beam and VSB writing in 12 hrs for 193i", Proc. SPIE 11327, Optical Microlithography XXXIII, 113270K (31 March 2020) [3] Yuansheng Ma, Le Hong, James Word, Fan Jiang, Vlad Liubich, Liang Cao, Srividya Jayaram, Doohwan Kwak, YoungChang Kim, Germain Fenger, Ananthan Raghunathan, Joerg Mellmann, “Reduction of Systematic Defects through Machine Learning from Design to Fab “, SPIE 11329-9 (2020)

Inverse Lithography techniques for mask optimization employ pixel based optimization algorithms and offer superior quality, but are compute intensive. A Machine learning model can be leveraged to replace the compute intensive portion of the ILT flow. In this paper we demonstrate that Machine learning models can be utilized to speed up the turnaround time of ILT flows. A CNN can be trained to compute an initial approximation of the mask, which can then be cleaned up using a few iterations of conventional OPC. We show that a performance gain of about 4X is achievable without any adverse impact on quality.

Subresolution assist feature (SRAF) insertion is an effective way to improve the printability and lithographic process window of isolated and semi-isolated features. State-of-the-art works resort to machine learning to reduce the computational cost associated with model-based methods. However, the result of SRAF probability learning, a probability map, cannot be directly treated as SRAFs. Inserting an SRAF to each layout grid predicted as 1 leads to design rule violations. Therefore, the SRAF probability learning model can only guide SRAF insertion and needs special handling to place SRAFs. For SRAF placement, we observe that placing SRAFs at probability maxima might be too greedy so that the SRAF prediction is masked to a certain extent. Therefore, we propose a novel methodology for SRAF placement over a machine learning generated probability map. First, a clustering-based method generates an initial SRAF inserted layout based on the given probability map. Then, a two-stage SRAF legalization strategy modifies the positions of SRAFs to be compliant with design rules. Experimental results show that given a probability map, our methodology can generate an SRAF inserted layout which guarantees design rule violation freeness while maintaining competitive PV band and EPE.

Matrix-OPC is used to mathematically derive mask bias using mask error enhancement factor (MEEF) matrix. Since MEEF denotes the edge placement error (EPE) change of segment induced by unit mask bias of its neighbor segment, exact MEEF calculation requires lithography simulation before and after perturbing neighbor segments. Therefore, MEEF calculation is a computationally expensive process, which leads to matrix-OPC being applied to only some critical regions in a layout. We propose fast MEEF prediction using an artificial neural network (ANN). MEEF represents the effect of one segment on another, so polar Fourier transform signals extracted from both segments are used as input of ANN. Also, the distance between two segments and the direction of each segment is used as input of ANN. Predicted MEEFs are used to construct MEEF matrices and matrix-OPC is used to derive mask biases. Experimental results show that proposed MEEF prediction is 3.7 times faster than exact MEEF calculation, thus matrix-OPC with predicted MEEFs is 30% faster than matrix-OPC with exact MEEFs.

With the algorithmic breakthroughs in machine learning, increasingly more applications have been developed for computational lithography. In this paper, a pixelated mask synthesis method including After Development Inspection (ADI) contour and mask feature generation, was proposed by utilizing deep learning technique. Two Generative Adversarial Networks (GANs) were constructed, the first network was for mask to contour prediction, and the consecutive network was to perform design to mask correction. A pix2pix model was first trained to learn the correspondences between mask image and paired ADI contour image collected on wafer, thus the capability of printing prediction can be established. The well trained mask-to-contour model was then implemented as the simulator component of machine learning mask correction (ML-OPC) framework. Next, another unsupervised GAN formed the front-end of ML-OPC framework to synthesize mask patterns from any given design layout. Generated mask patterns were eventually optimized through minimizing pixel difference between design target and corresponding contour generated by mask-to-contour model. The experimental results demonstrated that our ML-OPC framework can mimic conventional OPC model to produce exquisite mask patterns and contours.

The goal of this study is to discuss the findings of experiments we conducted to enhance defect capture rate in the advanced nodes design-for-manufacturing flow. As a metric of manufacturing excellence, wafer fabrication units track and report defect density on a regular basis. Fabrication with a reduced defect density can produce a higher chip yield. In recent years, systematic defects resulting from design and process have been predicted to be the leading cause of yield loss. This could result in a large rise in manufacturing costs and time. As a result, they are highly undesirable, and it is critical to accurately identify them for root analysis of weak patterns. Unlike random process defects, systematic patterning defects may show characteristic design features and our goal is to leverage these to create a machine learning model that can efficiently identify and categorize these defects before they get into production. An inherent problem that we face is class imbalance: high confidence defect data constitutes a few thousand samples for maturing nodes and nondefects of the order of millions. Additionally, millions of records in the train, test, and inference datasets, even with reduced feature sets, can lead to a host of big data issues like insufficient memory, large experiment times, and lack of integrated development. In this paper, we discuss methodologies to handle the large volume, imbalanced data which led to 47% improvement in the defect capture and 100% improvement in the noise to signal ratio.

Retargeting-aware Design for Manufacturability (DFM) via-metal enclosure checks are developed using supervised machine learning to identify critical weak points to aid layout fixing. The machine learning model is developed using a neutral network architecture. Seventeen localized layout features were extracted, including: side and line end via-metal enclosure, via spacing to the neighboring features, and metal coloring. The extracted features were used to form feature vectors to train and generate a machine learning-based model for predicting post-retargeting, via-metal enclosures. This method was demonstrated on 22nm layouts. Using a neural network with 2-hidden layers, the predicted via-metal enclosure versus the actual data correlate with an R2 of 0.91 and an RMSE 0.0067.

The Chemical Mechanical Polishing (CMP) variation on a die is a function of the die’s location on the wafer. For example, the post CMP thickness and/or topography variations in the center die can be very different from those in the mid-radius and edge dies. Consequently, the number of CMP hotspots and the hotspot locations can vary from die-to-die on a given wafer. Most commercial CMP simulation tools in the Design for Manufacturing (DFM) field focus on predicting CMP topography and thicknesses for a single die on the patterned wafer, and do not have wafer level prediction capabilities. For CMP simulation to be more effective in process and layout optimization, CMP simulation tools should be able to accurately predict CMP performance at the feature-scale, within the die, and across the entire wafer. In this paper, we analyze CMP data from multiple dies on back end of line (BEOL) Cu interconnect levels and show the wafer level effects in a polishing process. We use the data to calibrate Cadence’s integrated wafer level and die level CMP models and use the calibrated models to predict the CMP pattern dependencies on multiple dies across a product chip wafer. Finally, we show a comparison of the simulation to measured data.

Automated image analysis and image classification system that employs machine learning has been developed and applied to the PWQ/FEM flow to enhance the Process Stability Diagnosis (PSD) solution, which can now handle a significant volume of wafer images while realizing a 4X reduction in time to results. Moving the task of image analysis and classification to the computer has the added benefit of avoiding person-to-person inconsistencies in classification. The data flow consists of an automated machine learning-enabled process window analysis system that relies on CDSEM images taken on a FEM or Focus/Exposure Matrix wafer. We report results based on CDSEM images containing both contact hole and line features. The system enables full-wafer SEM image auto-classification and process window characterization.

With the technology node scaling to 5 nm, the forbidden pitch effect caused by destructive interaction between main feature and neighboring feature always leads to poor process window. Due to the small critical dimension (CD) and pitch of these features, forbidden pitches (FPs) become more sensitive in extreme ultraviolet (EUV) lithography. Therefore, controlling of FPs are becoming more and more critical. With the purpose of providing a strategy of mitigating the negative effect of forbidden pitch, an optimization method of the mask structure is developed in this paper. For illustration, three optimal mask structures under quasar illumination conditions are given by the optimized method. The performances of these three structures are demonstrated by the numerical lithography simulator S-litho. The effectiveness and validity of the proposed method are demonstrated from above simulation results. Therefore, the mask structure provided by the optimized method has the potential to be an efficient candidate for mitigating the negative effect of forbidden pitch structure.

In the mask data preparation (MDP) flow, it is necessary to verify that layout structures are correctly placed and that specific critical dimensions (CDs) are correct. Certain layout versions of Electrical Test (ETest) structures are placed throughout various locations of the frame data which will be sent for fracture and mask production. Within each ETest structure, there are many sub-structures and gauge points where we want to verify dimensions and locations in the post fractured data. The current preparation flow being employed is error-prone and time-consuming, considering that the entire verification process is done manually. To address this issue, we have utilized a novel pattern search methodology that can measure and report gauge locations relative to unique identifier pattern locations which can all be reviewed graphically on the actual mask data. A full inspection point kit is first generated by a developer using automation scripts which allow graphical gauge definitions relative to a unique identifier pattern per ETest location. A revision-controlled pattern library is created to define the test patterns to be measured based on the technology product. A user can then take this kit and run all post-fracture reporting of ETest structures per tape-out. Correspondence with the mask shop is also simplified and discrepancies are easily verified. In this paper, we will discuss in greater detail how this pattern-based approach and the utilization of pattern libraries help us in significantly reducing the possible errors and verification time. We will also review how the entire process which includes the location measurement and the reporting structure to the mask shop can be fully automated, hence, improving the productivity and the turn-around-time for the mask manufacturing process.

Forbidden pitches (FPs) effect is directly related to the loss of process window, which is caused by the difference of diffraction orders of patterns in some pitches. This paper analyzes the FPs effects in extreme ultraviolet (EUV) lithography based on the rigorous imaging simulation and process window evaluation. In the rigorous simulation, S-litho is used to analyze the normalized image log slope of test patterns from critical layer, which allow us to find the weak pitches. Then, the process windows of these test patterns are evaluated using the lithography simulator Proteus WorkBench. This can find out the accurate FPs from the range of weak pitches. Finally, the strategy of mitigating the negative effect of FPs is proposed with the help of source optimization. Unlike deep ultraviolet lithography, the difference of FPs between vertical and horizontal direction is presented in the paper. The simulation results have effectively been used design rules.

As critical dimension (CD) shrinks, the spec of CD uniformity (CDU) is getting tighter. To ensure CDU requirement, OPC team is making great efforts on etch proximity correction (EPC) than ever. For a long time, EPC only considers aperture effect which is usually simplified as a width and space rule table. However, astechnical nodes ever-shrinking, microloading effect plays a much more import role than aperture effect and rule table is not suitable any more. As in microloading effect pattern density is the key factor, we studied the density effect on dense array patterns with fixed CD and pitch in this paper. Firstly we designed a series of test pattern for calibrating an etch model, then we refined a simplified density rule table from the good fit (R2 >0.94) etch model. Contrast to traditional width/space rule table and complicated etch model, this approach is convenient and effective on dense array patterns EPC.

Optical Proximity Correction (OPC) is one of the most important techniques in improving the resolution and pattern fidelity of optical lithography in the semiconductor industry. As the feature sizes and the process margin in nanometer technology become smaller, OPC models also need to be more accurate. However, improving the model accuracy often requires collecting more SEM data, which in turn results in a longer time for the entire flow. Therefore, an efficient method that can improve the accuracy of the OPC model while reducing the data collection time is crucial. Furthermore, machine learning has recently been applied to the lithography optimizations with some success, so it will be a useful technique to further optimize gauge sampling. This paper proposes an efficient OPC model gauge sampling flow using machine learning methods through data preprocessing, feature transformation and clustering to divide sample data into clusters and select a small amount of representative sample data from them to calibrate the model, achieving the same effect as using all data to calibrate. In order to test and verify the proposed approach, we use various types of patterns including line-space, contact hole, etc., to verify our results. By optimizing the gauge sampling flow, we can reduce the gauge requirements and modeling run time without sacrificing the accuracy and stability of the model.

Beyond the 40nm technology node, layout weak points and hotspot types increase dramatically. Many hotspots can be detected by OPC simulation. However, in advanced nodes, OPC simulation suffers from a long turn-around-time (TAT) and is challenged to handle the additional design complexity. Therefore, in order to speed up the process and OPC development, an efficient OPC hotspot detection method is required. This paper presents a flow using Pegasus Computational Pattern Analytics (CPA) technology from Cadence to extract a comprehensive set of patterns to build a pattern bank from a layout source. We can then compare two or more different banks (diffing) to find new patterns which have not been processed before. OPC engineers can analyze these new patterns to check for any OPC issues instead of simulating a full chip. This flow provides a much higher efficiency and better performance while allowing the storage of pattern banks over time to build history and yield experience. Over time, each new layout introduced for OPC can be processed faster because more patterns have been added to the banks and less simulation time is needed.