Spin Orbit Torque (SOT) magnetic random-access memory (MRAM) offers the possibility to realize non-volatile ultra-high-speed technology. SOT-MRAM can also potentially reduce embedded memory footprint, which would inturn reduce silicon cost. However, there are certain challenges to overcome for SOT integration with logic. SOTMRAM needs a tall ‘VIA’ for the MTJ connection to the transistor. The height of this tall ‘VIA’ can vary from 60nm to 300nm for the N5 technology node. The VIA Critical Dimension (CD) depends upon metal width (30nm) which connects MTJ to read transistor. Thus, the aspect ratio needed for proper SOT integration is at least 10. This high aspect ratio is a major challenge for SOT integration, but it can be reduced (even down to 2) at the cost of SOT and MTJ stack integration complexity. On the other hand, keeping WL spacing constant and reducing WL width to facilitate increased MTJ connecting metal width (hence improve the AR for the same height) will increase the WL resistance. This WL resistance increment degrades WL delay as parasitic resistance is more problematic than capacitance at advanced nodes. In conclusion, while a tall VIA for SOT-MRAM has integration challenges due to the high VIA aspect ratio, mitigating this by means of wider VIA CD can potentially increase WL delay. Therefore, a comprehensive DTCO considering different bit-cells, SOT integration options and Memory performance is needed for SOT technology to be adopted at the most advanced technology nodes.
Buried power rail (BPR), a novel integration approach for further device scaling, brings in new patterning needs and requirements, the most importantly, the challenging middle-of-line (MOL) patterning process steps. In this paper, some of the critical plasma dry etch development processing results for the FinFET device flow with BPR integrated are presented. Mainly, the study was focused on plasma dry etch development of high aspect ratio Via contact to BPR metal (VBPR) and Trench contact etch (M0A) to the source/drain (S/D) device region. We demonstrate the short-free M0A (no attack on the neighboring gates) contact etch to the S/D, with the high etch selectivity values obtained in case of the dielectric SiO2 trench etch to the thin Si3N4 liner (deposited over epitaxial S/D), and subsequently the high selectivity values during SiN liner etch to the underlying S/D (SiN liner etch results in 0nm epitaxial film loss). Patterning of high aspect ratio (HAR) Via consisting of the multi-stack, SiO2/SiN/SiO2/SiN dielectric, landing on the bottom BPR metal was achieved, with the target critical dimension (CD) required to avoid shorting to the adjacent gates. Additionally, we report our learnings on how choice of buried power metal (W, Ru and Mo) impacts the etch requirements, i.e., the etch challenges associated by using Ru and Mo as a replacement for standardly used W metal.
As conventional pitch scaling is saturating, scaling boosters such as buried power rail (BPR) [1-4] and its extension to backside power delivery (BSPDN) [5, 6] could provide 20% and 30% area gain [7], respectively. BPR can also help to improve SRAM design [8] and is a building block in novel architectures such as CFET [9, 10], for technology scaling beyond the 3 nm CMOS node. The two main features of BPR technology include: (i) the introduction of BPR metal within the fin module (fig. 1). Metal insertion in front-end-ofline (FEOL) has a risk of tool/wafer cross-contamination. Ensuring that BPR metal is fully encapsulated during contamination critical processes such as epitaxy, is therefore, essential. A proper choice of metal limits the risk of device performance/reliability degradation from metal diffusion & mechanical stress. (ii) The addition of VBPR via connections from M0A contact level to the BPR lines. Its challenges include high aspect ratio (AR) patterning, achieving low resistance (R) and reliable contact with BPR. This paper reports an overview of BPR/Via-to-BPR (VBPR) module development and metallization options at BPR and VBPR.
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