KEYWORDS: Optical lithography, Metals, Etching, Transistors, Atomic layer deposition, Silica, Inspection, Electrodes, Transmission electron microscopy, System on a chip
The surrounding-gate-transistor (SGT) is a vertical gate-all-around device with a new design to exploit natural area gain for further scaling the SRAM size beyond N5 node. One of the benefits in SGT is it can fully decouple the dependency of the gate length (Lg) and the source/drain (S/D) contact size from the contact gate pitch (CGP) scaling, which is seen as a hard limit for the conventional scaling. To fully realize the benefit of area gain and Lg scaling independent from lithography, the patterning challenges of 3D vertical device structure must be resolved. In this paper, we report the MOL patterning challenges in SGT device fabrication, such as Metal recess process, Bottom Contact formation (VBG), Cross point formation (XC), Top electrode (TE) patterning.
As conventional pitch scaling is saturating, scaling boosters such as buried power rail (BPR) [1-4] and its extension to backside power delivery (BSPDN) [5, 6] could provide 20% and 30% area gain [7], respectively. BPR can also help to improve SRAM design [8] and is a building block in novel architectures such as CFET [9, 10], for technology scaling beyond the 3 nm CMOS node. The two main features of BPR technology include: (i) the introduction of BPR metal within the fin module (fig. 1). Metal insertion in front-end-ofline (FEOL) has a risk of tool/wafer cross-contamination. Ensuring that BPR metal is fully encapsulated during contamination critical processes such as epitaxy, is therefore, essential. A proper choice of metal limits the risk of device performance/reliability degradation from metal diffusion & mechanical stress. (ii) The addition of VBPR via connections from M0A contact level to the BPR lines. Its challenges include high aspect ratio (AR) patterning, achieving low resistance (R) and reliable contact with BPR. This paper reports an overview of BPR/Via-to-BPR (VBPR) module development and metallization options at BPR and VBPR.
While the semiconductor industry has reached the high-volume manufacturing of the 7 nm technology node (N7), patterning processes for future technology nodes N5, N3 and even below, are being investigated and developed by research centers. To achieve the critical dimensions of gratings for these future technology nodes, we require multipatterning approaches, such as self-aligned double/quadruple/octuple patterning (SADP/SAQP/SAOP) and multiple litho-etch (LE) patterning, in combination with 193i lithography and even EUV lithography. These gratings need to be subsequently cut or blocked, which is typically done by one or more block masks. As the edge placement error (EPE) budget drastically decreases with decreasing critical dimensions, the standard LE block patterning scheme is not sufficient anymore. To relax the EPE budget, dedicated scaling boosters are required such as the self-aligned block scheme, which defines blocks in trenches, selectively to the neighboring trenches.
In this work we explore the different multipatterning options for lines and blocks at pitches below 20 nm. As such, we will demonstrate and compare three different patterning options to enable 16 nm pitch gratings: 193i-based SAOP, EUV-based SADP and EUV-based SAQP. Finally, we will also elaborate on a self-aligned patterning scheme which does not define lines and blocks sequentially anymore but integrates them in a mixed mode. This patterning approach (SALELE) makes use of two LE masks and two self-aligned block masks. We will present its development status at relaxed pitch (28 nm) and discuss its advantages for future technology nodes.
There is a growing interest in new spin on metal oxide hard mask materials for advanced patterning solutions both in BEOL and FEOL processing. Understanding how these materials respond to plasma conditions may create a competitive advantage. In this study patterning development was done for two challenging FEOL applications where the traditional Si based films were replaced by EMD spin on metal oxides, which acted as highly selective hard masks. The biggest advantage of metal oxide hard masks for advanced patterning lays in the process window improvement at lower or similar cost compared to other existing solutions.
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