Environmental sustainability is at the core of many recent studies, offering research opportunities to help meet the ambitious net-zero commitments defined by semiconductor companies. In this context, it is important to analyze the sustainability challenges that different process areas are facing. To enable process engineers to develop sustainable solutions, new metrics, suitable tools and clear targets need to be provided. In this paper we analyze how such tools should be crafted to help the definition of sustainable practices for semiconductors processing.
The concurrent saturation in dimensional scaling and increase in manufacturing cost and complexity has caused the overall semiconductor manufacturing cost to significantly increase. As a result, the cost per transistor is predicted to sharply increase in future technologies, deviating from the typical 30% cost per transistor reduction. This work explores the use of 3D-integration technologies, as wafer-to-wafer hybrid bonding, for both mobile and high-performance application. It is observed that the use of 3D-integration schemes, can reduce the overall die cost at same functionality, paving the way for cost-effective scaling solutions in future technologies.
Future advanced semiconductor manufacturing processes are introducing significant patterning challenges. These challenges are coming together with additional requirements for sustainable, low Global Warming Potential/ low toxicity /low fine particle emissions. As a result, new solutions in terms of process integrations, molecules used for patterning modules, and overall stack of materials will have to meet those requirements while staying compatible with high-volume manufacturing (cost, availability, throughput, and overall patterning performance). Although specific process steps such as capacitor patterning for DRAM or 3D NAND high aspect ratio oxide etch are heavily scrutinized steps in terms of emissions and patterning challenges, many applications, including logic, integrate hundreds of steps where the patterning of 10 to 30nm-thick layers requiring fluorine-containing gases. Although independently accounting for a modest amount of emissions, their sheer counts makes them a major contributor to CO2 equivalent emissions. In this work, the cumulative impact of these low aspect-ratio patterning steps will be modelled through the imec.netzero program model. Then, the impact of a few sustainability-optimized solutions, such as low temperature etching for ultra-thin layer or stack optimization will be assessed.
Sustainability is gaining momentum as countries and companies announce targets for net-zero carbon emissions by 2050. imec has created a bottom-up model using tool data, process recipes, and integrated wafer process flows to create a virtual fab. With this model, it is possible to quantify the environmental impact of manufacturing integrated circuit (IC) chips for current and future logic and memory technology modes. In this paper, the model is used to identify areas with the highest environmental impact. It is important to reduce the impact of both lithography and etch since together they are responsible for 45% of total CO2 equivalent emissions associated with fabricating an N3 logic node wafer. For lithography, two approaches to reducing the environmental impact will be described: one concentrates on tool consumption and the other on process choices to maximize throughput. For etch, the focus is on reducing overall gas consumption and improving wafer material stacks to minimize fluorocarbon use. Translating patterning process changes into emission numbers will enable informed process choices for future and contribute to a shift towards net-zero semiconductor manufacturing.
KEYWORDS: Optical lithography, Metals, Etching, Transistors, Atomic layer deposition, Silica, Inspection, Electrodes, Transmission electron microscopy, System on a chip
The surrounding-gate-transistor (SGT) is a vertical gate-all-around device with a new design to exploit natural area gain for further scaling the SRAM size beyond N5 node. One of the benefits in SGT is it can fully decouple the dependency of the gate length (Lg) and the source/drain (S/D) contact size from the contact gate pitch (CGP) scaling, which is seen as a hard limit for the conventional scaling. To fully realize the benefit of area gain and Lg scaling independent from lithography, the patterning challenges of 3D vertical device structure must be resolved. In this paper, we report the MOL patterning challenges in SGT device fabrication, such as Metal recess process, Bottom Contact formation (VBG), Cross point formation (XC), Top electrode (TE) patterning.
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