Mr. Andy Yang Profile

Andy Yang

Senior Manager at ASML

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Publications (3)

Proceedings Article | 10 October 2019 Paper

Full-chip application of machine learning SRAFs on DRAM case using auto pattern selection

Kun-yuan Chen, Andy Lan, Richer Yang, Vincent Chen, Shulu Wang, Stella Zhang, Xiangru Xu, Andy Yang, Sam Liu, Xiaolong Shi, Angmar Li, Stephen Hsu, Stanislas Baron, Gary Zhang, Rachit Gupta

Proceedings Volume 10961, 1096108 (2019) https://doi.org/10.1117/12.2524051

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As technology continues to scale aggressively, Sub-Resolution Assist Features (SRAF) are becoming an increasingly key resolution enhancement technique (RET) to maximize the process window enhancement. For the past few technology generations, lithographers have chosen to use a rules-based (RB-SRAF) or a model-based (MB-SRAF) approach to place assist features on the design. The inverse lithography solution, which provides the maximum process window entitlement, has always been out of reach for full-chip applications due to its very high computational cost. ASML has developed and demonstrated a deep learning SRAF placement methodology, Newron™ SRAF, which can provide the performance benefit of an inverse lithography solution while meeting the cycle time requirements for full-chip applications [1]. One of the biggest challenges for a deep learning approach is pattern selection for neural network training. To ensure pattern coverage for maximum accuracy while maintaining turn-around time (TAT,) a deep-learning-based Auto Pattern Selection (APS) tool is evaluated. APS works in conjunction with Newron SRAF to provide the optimal lithography solution. In this paper, Newron SRAF is used on a DRAM layer. A Deep Convolutional Neural Network (DCNN) is trained using the target images and Continuous Transmission Mask (CTM) images. CTM images are gray tone images that are fully optimized by the Tachyon inverse mask optimization engine. Representative patterns selected by APS are used to train the neural network. The trained neural network generates SRAFs on the full-chip and then Tachyon OPC+ is performed to correct main and SRAF simultaneously. The neural network trained by APS patterns is compared with those trained by patterns from manual selection and multiple random selections to demonstrate its robustness on pattern coverage. Tachyon Hierarchical OPC+ (HScan+) is used to apply Newron SRAF at full-chip level in order to keep consistency and increase speed. Full-chip simulation results from Newron SRAF are compared with the baseline OPC flow using RBSRAF and MB-SRAF. The Newron SRAF flow shows significant improvements in NILS and PV band over the baseline flows. This whole flow including APS, Newron SRAF and full-chip HScan+ OPC enables the inverse mask optimization on full-chip level to achieve superior mask performance with production-affordable TAT.

Proceedings Article | 20 March 2019 Paper

Robust alignment mark design for DRAM using a holistic computational approach

Danying Li, Stella Zhang, Chia-Huang Chen, Youping Zhang, Alex Huang, David Xu, Yufeng Wang, Zhen Shi, Shi-lu Wang, Sheng-Tsung Tsao, Angmar Li, Andy Yang, Junwei Lu

Proceedings Volume 10961, 109610Z (2019) https://doi.org/10.1117/12.2532841

KEYWORDS: Optical proximity correction, Optical alignment, Semiconducting wafers, Optical lithography, Signal processing, Printing, Metrology, Overlay metrology

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Proceedings Article | 20 March 2018 Presentation + Paper

Freeform mask optimization using advanced image based M3D inverse lithography and 3D-NAND full chip OPC application

Yaobin Feng, Zhiyang Song, Moran Guo, Jun He, Longxia Guo, Gang Xu, Sam Liu, Jingjing Liu, Stephen Hsu, Austin Peng, Andy Yang, Rachit Gupta , Junwei Lu, Victor Peng, Jun Wang, Xiaolong Shi, Leon Liu, Rafael Howell, Cuiping Zhang , Zero Li, Ning-ning Jia

Proceedings Volume 10587, 105870G (2018) https://doi.org/10.1117/12.2297397

KEYWORDS: Photomasks, Source mask optimization, Optical proximity correction, Lithography, SRAF, Semiconducting wafers, Printing, Electroluminescence, Scanning electron microscopy, Pattern recognition

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Inverse lithography is increasingly being used as a viable OPC solution to maximize process window (PW), improve CD uniformity (CDU) and minimize the mask error factor (MEF), especially for memory devices. The device yield is typically limited by the process window of a few critical layers, and the Via layer is identified as one of the process window limiters for advanced 3D-NAND devices. To maximize the on-chip yield, ASML has developed advanced image based Mask-3D (M3D) inverse technology that can optimize freeform mask shapes and enhance design printability throughout the mask optimization flow. Mask rule checks (MRC) and side-lobe printing are optimized simultaneously to deliver the maximum process window.

The advanced image based M3D inverse lithography technology (ILT) is used to perform full chip mask correction on the Via layer of a 3D-NAND device. 3D NAND devices contain highly repetitive cell and page buffer patterns. To ensure the full chip device performance, the consistency of the mask correction is important. Our strategy is to use the computationally intensive mask optimization solution from the new advanced image based M3D inverse technology to generate a freeform mask which gives the best lithography performance. We then use Tachyon’s Pattern Recognition and Optimization (PRO) engine to propagate the freeform mask solution of the repetitive patterns to the full chip. The periphery of the chip is optimized using conventional OPC methods. The simulation results from the advanced image based M3D inverse technology are compared against the baseline flow, which uses a standard inverse solution. The simulation results from both the flows are further validated on wafer. Significant improvement in overlapping process window (OPW) and CD uniformity is observed using the new advanced inverse technology. The simulation data shows a 32% improvement in depth of focus (DOF), a 5% improvement in the image log slope (ILS) and a 25% reduction in best focus shift (BFS) range. The improvement has also been verified at the wafer-level.

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