In the initial stage of advanced packaging, it was applied to CSWLP (Chip-Scale-Wafer-Level-Package) mainly for the package form-factor reduction. However, advanced packaging is used not only for the package size reduction but also for many remarkable features including Fan-out wafer level packages that are used for mobile application processor to increase interconnect counts and reduce chip height. 2.5D silicon interposer technology is also used for Graphics Processing Units (GPU) and Artificial Intelligence (AI) chips to interconnect System-on-Chips (SoC) and cache memory to provide wide bandwidth. Advanced packaging will also play a key role in the upcoming heterogeneous integration. Canon developed the first i-line stepper for advanced packaging in 2011. Since then, we have expanded our tool lineup to support customer demands with developments supporting large size packages and panel-level packaging. In this paper, we compare advantages between wafer-level packaging and panel-level packaging. Furthermore, we will report our low distortion patterning solution of our latest packaging stepper, FPA-5520iV LF2 option.
Advanced packaging was applied during the early stages of CSWLP (Chip-Scale-Wafer-Level-Package) development for mainly package form-factor reduction. However, advanced packaging is used not only for package size reduction but also for many remarkable features including fan-out wafer level packages that are used for mobile application processor to increase interconnect counts and reduce chip height. 2.5D silicon interposer technology is also used for Graphics Processing Units (GPU) and Artificial Intelligence (AI) chips to interconnect System-on-Chips (SoC) and cache memory to provide wide bandwidth computing power. Advanced packaging will also play a key role in the upcoming Chiplet era. Canon developed our first i-line stepper for advanced packaging in 2011. Since then, we have expanded our tool lineup to support customer demands with developments supporting large size packages and panel-level packaging. In this paper, we compare advantages between wafer-level packaging and panel-level packaging. In addition, we study bonding error budgets for fine pitch bump package in the upcoming Chiplet era. We will compare bonding errors among Silicon interposers, Organic interposers, and Glass interposers and point out the importance of lithography tool distortion reduction to realize less than 10 µm bump pitch packages. Furthermore, we will report on our low distortion patterning solution, the FPA-5520iV LF2 advanced packaging stepper.
Demand for advanced graphics processing unit, field programmable gate array, and artificial intelligence (AI) chips continues to grow as many systems require more computing power for applications, such as AI processing and deep learning. To produce higher-performance chips, 2.5D silicon interposer technology has been developed and matured as a solution enabling high-speed data transmission between different chips, such as processors and dynamic random access memory. Increased I/O counts are required to enable higher bandwidth communication between semiconductor chips and silicon interposers can help realize higher-performance devices. Microbumps used to interconnect chips and interposers and redistribution layer must be scaled down to achieve high-density connections and next-generation devices also require larger interposers to support heterogeneous integration of multiple dies. We highlight the performance of the FPA-5520iV LF2-option stepper that is designed to provide the optimal stepper performance required for the next generation 2.5D interposers, including submicron resolution, high-accuracy mix-and-match overlay, and large field exposure.
Heterogeneous integration is evolving to acquire finer resolution and larger devices to leverage the advantages provided by more-than-Moore manufacturing and packaging technologies that can help maximize the efficiency and increase the bandwidth of high performance computing systems. 2.xD integration with redistribution layers and large package sizes is one of solutions that can enable complex heterogeneous integration designs for applications, including artificial intelligence, 5G communication, and autonomous driving. For systems requiring large package sizes, panel level packaging (PLP) can offer efficiency and cost advantages over wafer level packaging. PLP, however, poses unique technical challenges, including the requirement to realize uniform fine patterning across the entire rectangular panel. In this paper, we report on our study of resolution and overlay performance using the panel stepper including an introduction of technology innovations supporting 2.xD heterogeneous integration development.
Heterogeneous Integration is one “More-than-Moore” strategy that can help continue the trend towards overall electronics system scaling and cost reduction. Heterogeneous Integration involves high-efficiency and high-density interconnection of multiple chiplets and/or dies using advanced packaging technologies to provide communication bandwidth beyond what can be accomplished through circuit scaling alone.
This paper introduces the FPA-5520iV and FPA-8000iW steppers that are designed to meet the requirements of sub-micron Heterogeneous Integration applications. Topics include warped substrate handling, panel substrate processing, die-by-die overlay of highly distorted substrates, high-fidelity imaging across large exposure fields and high-accuracy stitching for exposure fields larger than 1 reticle.
KEYWORDS: Data modeling, Semiconducting wafers, Overlay metrology, Machine learning, 3D modeling, Lithography, Data acquisition, Wafer testing, Target detection, Process modeling
As a part of the semiconductor manufacturing process, an overlay measurement instrument is used to inspect overlay accuracy after exposure. The overlay measurement results are not only used to evaluate accuracy, but also to optimize exposure processing by calculating various offsets based on the measurement results and feeding them back to the exposure system. Increasing the number of overlay measurement points can help identify and compensate for local distortions including EPE (edge placement errors). However, it is not practical to perform overlay measurement for all wafers and all regions, therefore the better strategy for is performing correction through combining predicted results with actual measurement results. Canon is working with Macronix to develop the VMOM (Virtual Machine Overlay Metrology) system for predicting overlay measurement results. The VMOM method uses machine learning to study large amounts of data to derive the relationship between overlay error results and exposure system process variables that cause overlay error. A VMOM model was developed using 3D-NAND process data and overlay prediction accuracy and exposure process optimization were evaluated. This paper reports the development status of the VMOM system and the practical effects of the system.
Canon's CMOS sensor technology offers OEMs and end users expanded possibilities for industrial vision applications. From uniquely large pixel sizes to exceptionally high pixel counts in a compact design, Canon CMOS sensors push the boundaries of imaging possibilities. Facilitating on-going innovation in industrial camera and image capture technologies, Canon CMOS sensors support pioneering solutions for advanced industrial, machine vision, medical and scientific applications.
Semiconductor manufacturing equipment must maintain high productivity and provide high-yield processing and Canon has developing high-reliability exposure tools that have demonstrated high-uptime and performance stability in production. As global emergency epidemic restrictions limit the travel of expert engineers, customer service becomes more challenging and alternative methods of support are being developed to help customers meet their production roadmaps. To help control performance, lithography tools have sophisticated logging systems that can monitor every movement in the tool and we studied a novel Artificial Intelligence system that utilizes big logging data to help improve exposure tool uptime, productivity and performance related to yield. One goal of our study is to minimize exposure tool downtime by monitoring and reacting to tool status. For this purpose we are applying machine learning to develop abnormality detection or prediction models with automated recovery procedures for each abnormality. We will report on Auto-Fault-Tree-Analysis (FTA) models being constructed to evaluate large volumes of design and trouble information to help minimize downtime. Another study goal is to improve lithography tool performance by monitoring and reacting to factors including overlay accuracy and CD uniformity that can strongly affect device yield. Outputs of this analysis include simulation and optimization of equipment performance, and virtual metrology. This paper reports on the system we are developing to help increase the uptime, productivity and imaging performance of Canon semiconductor lithography tools. The system is designed to monitor the operating state of lithography tools and apply automated recovery and optimization actions identified through machine learning.
More-than-Moore approaches to improve system performance have been a hot topic for a more than a decade as a way to maximize the efficiency and increase the bandwidth of high performance computing systems. Fan-Out packaging that realizes submicron Redistribution Lines (RDL) and large die sizes is one technology that can help enable complex heterogeneous integration for applications including Artificial Intelligence (AI) and autonomous driving. For systems requiring large package sizes, Panel Level Packaging (PLP) can offer efficiency and cost advantages over Wafer Level Packaging (WLP). PLP however poses unique technical challenges including the requirement to realize uniform submicron patterning across the entire rectangular panel. To meet this challenge, Canon developed the first patterning exposure tool (stepper) capable of submicron resolution on 500 mm panels. The panel exposure tool is equipped with wide-field projection optics that offer a large 52 mm × 68 mm image field and a 0.24 NA that is optimum for submicron resolution. The stepper also features an updated panel handling system for processing up to 515 × 515 mm panels. In this paper, we will report on our study of fine patterning on rectangular panels using the submicron resolution panel stepper and will introduce technology innovations supporting advanced heterogeneous integration. Our study researched photoresist material performance and slit-coating uniformity challenges we identified through collaboration with resist vendors and slit-coating equipment manufacturers. We will report on the results of our collaborative study and will discuss current and future PLP advantages, challenges and solutions.
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