On-product overlay (OPO) is a critical inline process control parameter in semiconductor manufacturing. One of the main factors that induce the overlay error is non-lithography processes like etching, deposition and cleaning. The overlay margin is getting tighter as the device technology advances and detecting the root cause of process-induced overlay error is a main problem to improving the OPO. However, it is not an easy problem to solve due to the lack of inline monitoring data on non-lithography processes. Even if we evaluate inline monitoring data, it is too sparse to do in-depth analysis compared to abundant lithographic overlay data. Instead, we can make use of data from the PWG patterned wafer geometry metrology system, which can measure high-density data with high throughput. In this paper, we introduce a comprehensive method of detecting the root cause of the process-induced overlay errors based on inline PWG data. Our target device is a 3D NAND product with process-induced overlay errors due to wafer geometry. We start our analysis by tracing PWG GEN3 data for the same wafer in a wide process step range. We compare the GEN3 signature to an overlay error signature of a target lithography layer to filter out suspicious processes. From the suspicious processes, we derived optimized KPIs that discriminate between good and bad wafers in terms of process-induced overlay errors, which are then used as a monitoring metric. With the optimized KPIs, we discern which process is the root cause of process-induced overlay errors to help drive corrective actions and improve OPO on the target device. Finally, we propose a comprehensive framework that is not limited to PWG data but applies to other available inline data such as alignment, ADI and AEI overlay and NZO.
As the cell size of memory devices continues to shrink, tighter On-Product Overlay (OPO) specifications toward a 1nm OPO budget are required. EUV (extreme ultraviolet lithography) production was adopted in 2019 and the next lithography development known as High NA EUV will fulfill market demand beyond 5nm and 3nm process nodes. High NA EUV requires shrinking the scribe line from 50μm to 40μm, which results in new requirements for the target size to be smaller than the current size μDBO (16x16μm) and AIM (24x24μm) targets. The reduction in the scribe line is certainly beneficial to chipmakers for wafer real estate and yield. For metrology measurements in high-volume manufacturing (HVM), the main optical overlay (OVL) metrology usually uses imaging-based overlay (IBO) technology, while in other cases diffraction-based overlay (DBO) and scatterometry-based overlay (SCOL) are used. All methods (IBO, DBO, and SCOL) face the same challenge of target size reduction. For instance, IBO targets require a restricted number of grating bars. Most importantly, the smaller the target size, the less kernel information affects measurement quality. The spot size of DBO is larger than the target size, so it increases noise sources from the target's surroundings and affects the OVL accuracy. SCOL technology offers several advantages over IBO and DBO when measuring small targets since the spot size in SCOL is smaller and the spot navigation has a higher control mechanism. In this paper, we present a method called parallax to measure a single-cell overlay using pupil information. We will demonstrate three values: First, the target size can be reduced by up to half. Second, the measurement time is improved by saving navigation time from cell to cell. Third, the optical z-value for each point is reported along with OVL measurements. Additionally, the feasibility of single-cell OVL measurement and optical z-value is demonstrated as KPIs for process control.
KEYWORDS: Overlay metrology, Semiconducting wafers, Advanced process control, Scanners, Scatterometry, Process control, Signal processing, Metrology, Control systems, Optical parametric oscillators
As the cell size of memory devices continues to shrink, tighter on-product overlay (OPO) specs require more accurate and robust overlay control. The overlay error budget mainly consists of the reticle, scanner, process, and metrology errors. The metrology budget is generally required to be <10% of the OPO control budget so that the accuracy and robustness of overlay metrology become more crucial as pattern size gets smaller on current 1x nm DRAM nodes. For overlay control in high-volume manufacturing (HVM), the primary optical overlay metrology typically used is Image-Based Overlay (IBO). In many cases, scatterometry overlay (SCOL), using a direct grating-scanning method, was shown to achieve more accurate After Development Inspection (ADI) overlay measurements. Using a tunable source and customized illumination pupil to directly scan within the grating cell, this technology improves accuracy by reducing the contribution of pattern surroundings in the scribe line, resulting in improved OPO control stability. Since the purpose of overlay control is to minimize actual device pattern misregistration, as measured after the etching process (AEI), achieving accurate and stable characterization of the systematic deviation between ADI and AEI overlay known as Non-Zero-Offset (NZO) is critically important. Accurate NZO applied to the scanner via the Advanced-Process-Control (APC) loop enables effective scanner overlay control at the post-lithography ADI step. This paper demonstrates a new scatterometry overlay technology adopted in DRAM use cases that resulted in OPO and NZO stability improvement. In addition, we demonstrate an efficient method to monitor HVM run-to-run overlay performance and NZO stability by comprehensive dataset modeling combining ADI and AEI.
As DRAM technology continues to evolve, advanced nodes shrink the device dimensions and raise the requirements for on-product overlay control to reduce residual error. Increased process complexity also demands tighter accuracy and robustness in metrology control, which necessitates new and innovative metrology enhancements and methods. Scatterometry-based overlay (SCOL®) metrology is a unique overlay metrology architecture that uses angle-resolved pupil imaging for overlay analysis and calculation. KLA’s SCOL metrology system offers wide-spectrum tunable laser and multi-wavelength (MWL) illumination patterns along with custom-designed advanced algorithms that provide multiple measurement conditions to meet unique layer and target requirements. This paper demonstrates improved overlay metrology accuracy and residual error on DRAM FEOL critical layer with SCOL technology. Multiwavelength and rotated quadrupole (RQ) illumination in the metrology tool are utilized to provide significantly improved residuals compared with the traditional single-wavelength (SWL) and on-axis illumination.
Critical dimension uniformity (CDU) control using dose correction is well established and has relied on traditional polynomial models like Zernike and Legendre for a long time. As process margins are shrinking and CD (and CDU) control becomes a significant contributor to edge placement error (EPE), the dose correction models need to be enhanced to represent the systematic behavior of the fingerprints more precisely. In this paper we show that many CD signatures over the exposure field or over the wafer cannot be corrected efficiently using classical polynomials. As the CD signatures can come from a variety of processes like etch, CVD, polish, or deposition, a flexible model approach is required. Furthermore, making the right decision when choosing the correct model order of the classical polynomial based model is complicated as we need to handle the balance between the degrees of freedom and minimizing the residuals. With this problem statement in mind, we introduce a novel radial basis function (RBF) modeling approach for dose corrections that can correct a wide range of signatures. The new modeling approach is verified on real CD signatures on product, reducing CDU significantly. Additionally, we demonstrate that this approach can make the life of the engineers easy again, as there are no prior decisions about model type and order needed.
In the leading-edge production measuring the geometrical dimensions with e-beam inspection (CD-SEM data) or scatterometry technology (OCD data) is one of the most time-consuming steps without adding value to the wafer. Hence the fabs want to limit the effort to minimize the costs per wafer. On the other hand, the output of the metrology steps is needed to feed the SPC and APC systems with sufficient information. We handle that trade-off with a new sampling scheme optimizer supporting CD-SEM and OCD data.
Generally, we can use the sampling scheme optimization for a set of different features and their measured parameters in parallel. Especially in logic, but also for memory, the focus and dose dependencies of several features may be different. Hence, we optimized the distribution of the measured sites to create a perfect representation of the systematic fingerprint for all important anchor features within one single sampling scheme.
For the verification of the approach we investigated two cases. The first case are dense CD measurements, which are usually needed to create and update intra-field dose corrections. We minimize the number of measured sites significantly and distribute the remaining sites over different fields to ensure a good coverage of the systematic effects. Finally, that allows us a much higher update frequency of the dose corrections and yields in smaller CDU values.
The second case optimized the throughput of an OCD metrology system. The applied high-density sampling scheme for the focus monitoring done on reference wafers takes a lot of time during measuring. That specific type of measurement is done for monitoring and updating the focus reference corrections. With our proposed solution, we can achieve the same quality with respect to the reference measurement with more 50% less measured sites.
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