Nanoimprint lithography (NIL) is considered to be a sustainable technology for fabricating fine patterns and 3D structure of semiconductor devices. In this paper, we report preliminary results of device qualification for dual damascene structure fabricated by NIL. We have optimized NIL conditions to improve defectivity and overlay accuracy, and etching condition to improve fidelity and uniformity of 3D shape on the entire wafer. The 1st electrical characteristic results confirm the possibilities of one step fabrication of 3D dual damascene structure using NIL
Nanoimprint lithography (NIL) has received attention as alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost. Application of NIL may lead to the reduction of number of process steps and cost of manufacturing of dual-damascene structure, by simultaneous fabrication of holes and trenches. Therefore, in this study, we investigated fabrication of dual-damascene structure using NIL and dry-etching. However, the difficulty in dry-etching process is high as the holes and trenches are etched together using single resist mask. Suppression of defects during the NIL process and the suppression of resist consumption and CD shift during the etching process, is critical. To address these issues, we used a high etching resistance resist, optimized the NIL process to reduce defects, and optimized the template structure and etching process to suppress resist consumption and CD shift. As a result, a dual-damascene structure with L/S = 4X/4X nm was obtained.
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