In this paper the use of the EPE metric directly in the process optimization method for a DRAM use case has been researched. We show that EPE-aware optimization, using scanner dose and overlay control sub-recipes, is outperforming conventional optimization in terms of EPE Dies in Spec. Hence, it can be expected that also device yield can be improved by EPE-aware control.
Improvements on on-cell overlay is necessary to suppress misalign induced defects. Precise and accurate on-cell overlay measurements are strongly demanded, however, we are facing limitations on conventional CD-SEM based on-cell overlay measurements, such as unexpected overlay bias. To mitigate drawbacks of top view based on-cell overlay measurements, we present voltage contrast based overlay measurements (VCBO) which utilize specially designed cell patterns with combinations of programmed misalignments on scribe lanes, measured by defect inspection equipment, eP5 [1]. We successfully demonstrate the first defect based overlay measurement on DRAM device and a potential of 27% in-die overlay gain is shown. Also, we display overlay process margin at about ~1000 points on wafer. As a definite standard of on-product overlay measurement, this technology will be used for advanced misreading correction (MRC). We believe that the technique would be widely used and become necessary in near future.
In leading edge patterning processes, overlay is now entangled with CD including OPC residuals and stochastics. This combined effect is a serious challenge for continued shrink and can be characterized with an Edge Placement Error (EPE) budget containing multi-domain components: global and local CD, local placement errors, overlay errors, etch biases and OPC. EPE defines process capability and ultimately relates to device yield. Understanding the EPE budget leads to efficient ways to monitor process capability and optimize it using EPE based process control applications. We examine a critical EPE use case on a leading edge DRAM node. We start by constructing and verifying the EPE Budget via densely sampled on-product in-device local, global CD and Overlay metrology after the etch process step. EPE budget contributors are ranked according to their impact to overall EPE performance and later with simulated EPE performance improvements per component. A cost/benefit analysis is shown to help choose the most HVM-friendly solutions.
Shrinking pattern sizes dictate that scanner-to-scanner variations for HVM products shrink proportionally. This paper shows the ability to identify (a subset of) root causes for mismatch between ArF immersion scanners using scanner metrology. The root cause identification was done in a Samsung HVM factory using a methodology (Proximity Matching Budget Breakdown or PromaBB) developed by ASML. The proper identification of root causes-1 helps to select what combination of scanner control parameters should be used to reduce proximity differences of critical patterns while minimizing undesirable side effects from cross-compensation. Using PromaBB, the difference between predicted and measured CD mismatch was below 0.2nm. PromaBB has been proposed for HVM implementation at Samsung in combination with other ASML fab applications: Pattern Matcher Full Chip (PMFC), Image Tuner and FlexWave.
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