For advanced technology nodes, it’s critical to utilize resolution enhancement technique (RET) methods to improve pattern fidelity and wafer yield. Conventional techniques including rule-based SRAF (RB-SRAF) and model-based SRAF (MBSRAF) methods have been widely adopted to increase the manufacturing process window. ILT delivers superior imaging performance compared to both RB-SRAF and MB-SRAF methods, at the expense of slower performance and more inconsistency issue. Recent advancement of machine learning techniques opens up new gateways for more RET enhancements by overcoming these challenges, thus providing a pathway to extend ILT solution to full chip design. In this paper, we developed an end-to-end flow that seamlessly incorporated model training and application for full chip ILT MBSRAF generation and optimization via POLY-GAN, a new Generative Adversarial network (GAN) geared for fast, in-context and accurate ILT MB-SRAF synthesis. An image based deep learning architecture similar to pix2pix conditional GAN was utilized in our study. In this paper, we demonstrate that ML based full chip ILT MBSRAF generation yields superior process window compared to rule based SRAF generation, while maintaining comparable run-time performance.
For advanced technology nodes, it’s critical to address yield issues caused by process specific layout patterns with limited process window. RETs such as Model-Based Sub-Resolution Assist Feature (MB-SRAF) are introduced to guarantee high lithographic margin, but these techniques come with long runtime, especially when applied full-chip. There’s also lack of integrated solution to easily identify, define comprehensive patterns and apply different controls and/or constraints over these patterns through different stages of OPC/RET process.
In this paper, we introduce a flow that applies advanced RET such as MBSRAF or specific local corrections to layouts with critical and yield limiting patterns. We also introduce in-process pattern match based on Cadence topological Squish pattern. Overall, this new flow of Pattern-Aware OPC (PA-OPC) achieves better margin for hotspots, without sacrificing turnaround time and is able to handle more complex patterns and environment than traditional methods. We demonstrate the benefit of the new flow with fine-grained process window control over different patterns.
It’s critical to address the yield issues caused by process specific layout patterns with limited process window. RETs such as PWOPC are introduced to guarantee high lithographic margin, but these techniques cost high run-time when applied to full-chips. There’s also lack of integrated solution to easily identify, define comprehensive patterns and apply different controls and/or constraints over these patterns through different stages of OPC/RET process. In this paper, we study a pattern aware OPC flow that applies PWOPC or specific corrections locally to layouts with critical and yield limiting patterns. Although the full chip PWOPC provides an effective way, it causes great amount of run time penalty and does not achieve optimal process window. Overall, PAOPC achieves the better margins over the hotspots, without sacrificing turnaround time. The study demonstrates the benefit of the new flow with fine grained process window controls over different patterns. This flow get good improvement on defect counts when evaluated on 50 nm node logic devices.
In recent years, mask critical dimension (CD) linearity and uniformity has become increasingly important. The ITRS roadmap shows the mask CD control requirements exceeding those of the wafer side beyond the 45nm node. Measurements show that there are systematic, uncorrected proximity effects even when a state-of-the-art proximity effect correction (PEC) algorithm is used. The uncorrected proximity effect is predictable with a computational model. The model for e-beam lithography and etch process contains terms to model short-range pattern density effects and plasma shadowing effect in Cr-etch. The model is calibrated using CD measurements on a test mask. The model is valid for arbitrary 2-D patterns. We present a model-based mask process compensation (MPC) method which applies geometric changes to polygons as in OPC. We discuss the goodness of model fit to the calibration data; verification of the calibrated model by SEM images; and the improvement obtained by MPC. The mask writing error, i.e. final inspection CD minus incoming database CD, was reduced by a factor of 2 through the use of MPC.
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