Proceedings Article | 16 July 2002
KEYWORDS: Semiconducting wafers, Sensors, Critical dimension metrology, Photoresist materials, Temperature metrology, Optical lithography, Wafer testing, Photoresist developing, Silicon, Deep ultraviolet
The Post-Exposure Bake (PEB) is one of the critical pattern transfer steps in deep ultra-violet 248nm, 193nm (DUV) photolithography. The objective of the PEB is to activate the photo-acid produced during the exposure, which, in a self-catalyzing sequence, attacks the bonds of the organic compounds within the resist, making them soluble to the developer solution. This sequence generates more photo-acid, and the cycle continues until the process self-quenches. The acid is also rapidly diffusing along its concentration gradients, further impacting the final dimensions of the resulting pattern. All these phenomena are very sensitive to the PEB temperature trajectory, especially during the early stages of the process. Using existing state of the art equipment calibrated specifically to measure PEB effects, it has been reported that as much as 30 percent of the critical dimension (CD) error budget is due to the PEB variations from plate to plate or across one plate. Virtually all practical PEB procedures call for the rapid heating of the wafer to a recommended target temperature and time, followed by the rapid cooling down to near room temperature. The temperature and timing of the PEB and subsequent cooling are optimized for the particular photoresist chosen for processing. Due to the transient nature of the post exposure bake, aspects such as time-to-temperature, temperature overshoot, as well as steady-sate behavior must be measured, understood, and optimized in order to improve CD control, while minimizing, and if necessary, accommodating any variation across the PEB plate. Until recently, reliable measurements of the actual PEB temperature trajectories have been difficult to obtain. The PEB temperature mapping system provided by OnWafer Technologies allows for these conditions, since it is capable of processing inside the lithography track system as if it were a product wafer due to its design and its wireless nature. Furthermore, it has more than 40 rapid response sensors spread across the wafer surface, and thermal mass close to that of a product wafer. In this way, it can collect the temperature as a function of time during loading, transporting, heating and cooling, and it can provide an accurate view of the thermal history across the surface of a wafer. This information, coupled with physical models of the equipment and of the process can be used to more accurately characterize PEB behavior and its impact in CD control. Experiments done to date using the OnWafer system confirm that typical PEB steps can be too short for reaching steady-state conditions. More specifically, state of the art bake plates were found to require several seconds to heat a typical wafer within a degree of the target temperature, and they can overshoot the target temperature by a degree or more. Moreover, these plates may need a few minutes to stabilize within 0.1 degrees C from that target. Similar time constants apply during the cooling sequence. Experiments involving detailed gate layer CD measurements further validate the hypothesis that transient effects are responsible for much of the CD errors due to PEB, especially since these transient effects have a traceable non-uniformity. This paper will highlight the metrology involved in detecting PEB non-uniformities, demonstrate how the results of real-time post exposure bake data collection differ from 'static bake data test' collection and provide in-line bake data alongside collected CD data.
